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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Devanathan, V.R. Ravikumar, C.P. Kamakoti, V. |
| Copyright Year | 2007 |
| Description | Author affiliation: ASIC, Texas Instruments India Pvt. Ltd., Bangalore (Devanathan, V.R.; Ravikumar, C.P.) |
| Abstract | With increasing use of low cost wire-bond packages for mobile devices, excessive dynamic IR-drop may cause tests to fail on the tester. Identifying and debugging such scan test failures is a very complex and effort-intensive process. A better solution is to generate correct-by-construction "power-safe" patterns. Moreover, with glitch power contributing to a significant component of dynamic power, pattern generation needs to be timing-aware to minimize glitching. In this paper, we propose a timing-based, power and layout-aware pattern generation technique that minimizes both global and localized switching activity. Techniques are also proposed for power-profiling and optimizing an initial pattern set to obtain a power-safe pattern set, with the addition of minimal patterns. The proposed technique also comprehends irregular power grid topologies for constraints on localized switching activity. Experiments on ISCAS benchmark circuits reveal the effectiveness of the proposed scheme |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 160620 |
| Page Count | 6 |
| File Format | |
| ISBN | 9783981080124 |
| DOI | 10.1109/DATE.2007.364648 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-04-16 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | ESCI |
| Subject Keyword | Power generation Test pattern generators Testing Delay Packaging Timing Hazards Application specific integrated circuits Instruments Computer science |
| Content Type | Text |
| Resource Type | Article |
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