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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Garg, S. Marculescu, D. |
| Copyright Year | 2007 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA (Garg, S.; Marculescu, D.) |
| Abstract | Manufacturing process variations are the primary cause of timing yield loss in aggressively scaled technologies. In this paper, we analyze the impact of process variations on the throughput (rate) characteristics of embedded systems comprised of multiple voltage-frequency islands (VFIs) represented as component graphs. We provide an efficient, yet accurate method to compute the throughput of an application in a probabilistic scenario and show that systems implemented with multiple VFIs are more likely to meet throughput constraints than their fully synchronous counterparts. The proposed framework allows designers to investigate the impact of architectural decisions such as the granularity of VFI partitioning on their designs, while determining the likelihood of a system meeting specified throughput constraints. An implementation of the proposed framework is accurate within 1.2% of Monte Carlo simulation while yielding speed-ups ranging from 78times-260times, for a set of synthetic benchmarks. Results on a real benchmark (MPEG-2 encoder) show that a nine clock domain implementation gives 100% yield for a throughput constraint for which a fully synchronous design only yields 25%. For the same throughput constraint, a three clock domain architecture yields 78% |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 158103 |
| Page Count | 6 |
| File Format | |
| ISBN | 9783981080124 |
| DOI | 10.1109/DATE.2007.364625 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-04-16 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | ESCI |
| Subject Keyword | Throughput Voltage Clocks Frequency Delay Timing Circuits Computer aided manufacturing Design engineering Manufacturing processes |
| Content Type | Text |
| Resource Type | Article |
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