NDLI: Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign

Content Provider	IEEE Xplore Digital Library
Author	Ren-Jie Lee Ming-Fang Lai Hung-Ming Chen
Copyright Year	2007
Description	Author affiliation: Dept. of Electron. Eng. & SoC Res. Center, Nat. Chiao Tung Univ., Hsinchu (Ren-Jie Lee)
Abstract	Deep submicron effects drive the complication in designing chips, as well as in package designs and communications between package and board. As a result, the iterative interface design has been a time-consuming process. This paper proposes a novel and efficient approach to designating pin-out for flip-chip BGA package when designing chipsets. The proposed approach can not only automate the assignment of more than 200 I/O pins on package, but also precisely evaluate package size which accommodates all pins with almost no void pin positions, as good as the one from manual design. Furthermore, the practical experience and techniques in designing such interface has been accounted for, including signal integrity, power delivery and routability. This efficient pin-out designation and package size estimation by pin-block design and floorplanning provides much faster turn around time, thus enormous improvement in meeting design schedule. The results on two real cases show that our methodology is effective in achieving almost the same dimensions in package size, compared with manual design in weeks, while simultaneously considering critical issues in package-board codesign. To the best of our knowledge, this is the first attempt in solving flip-chip pin-out placement problem in package-board codesign.
Starting Page	804
Ending Page	809
File Size	982385
Page Count	6
File Format	PDF
ISBN	1424406293
DOI	10.1109/ASPDAC.2007.358088
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-01-23
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Signal design Electronics packaging Pins Process design Geometry Costs Time to market Design engineering Lead Printed circuits
Content Type	Text
Resource Type	Article

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