NDLI: High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Deming Chen Jason Cong Yiping Fan Zhiru Zhang
Copyright Year	2007
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana-Champaign, IL (Deming Chen)
Abstract	In this paper, we present a simultaneous resource allocation and binding algorithm for FPGA power minimization. To fully validate our methodology and result, our work targets a real FPGA architecture - Altera Stratix FPGA, which includes generic logic elements, DSP cores, and memories, etc. We design a high-level power estimator for this architecture and evaluate its estimation accuracy against a commercial gate-level power estimator - Quartus II PowerPlay Analyzer. During the synthesis stage, we pay special attention to interconnections and multiplexers. We concentrate on resource allocation and binding tasks because they are the key steps to determine the interconnections. We use a novel approach to explore the design space. Experimental results show that our high-level power estimator is 8.7% away from PowerPlay Analyzer. Meanwhile, we are able to achieve a significant amount of power reduction (32%) with better circuit speed (16%) compared to a traditional resource allocation and binding algorithm.
Starting Page	529
Ending Page	534
File Size	9000737
Page Count	6
File Format	PDF
ISBN	1424406293
DOI	10.1109/ASPDAC.2007.358040
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-01-23
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Space exploration Field programmable gate arrays Multiplexing Resource management Integrated circuit interconnections High level synthesis Delay Registers Power generation Logic
Content Type	Text
Resource Type	Article

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