NDLI: Communication Architecture Synthesis of Cascaded Bus Matrix

Content Provider	IEEE Xplore Digital Library
Author	Junhee Yoo Dongwook Lee Sungjoo Yoo Kiyoung Choi
Copyright Year	2007
Description	Author affiliation: Seoul Nat. Univ. (Junhee Yoo; Dongwook Lee)
Abstract	For high frequency on-chip communication architecture design, we propose cascaded bus matrix-based solutions. Due to the huge design space in cascaded bus matrix design, it is crucial to perform an efficient design space exploration. In our work, we present a simulated annealing-based design space exploration method. For an efficient representation of bus topology, we propose an encoding method called traffic group encoding and apply it to AMBA3 AXI-based bus system design. In addition, we propose a method of two-step simulated annealing to improve the quality of results. Experimental results show that the proposed methods allow designing complex communication architectures (ones with up to 31 masters and 71 slaves) with high frequency constraints to which existing methods could not give solutions.
Starting Page	171
Ending Page	177
File Size	9123188
Page Count	7
File Format	PDF
ISBN	1424406293
DOI	10.1109/ASPDAC.2007.357981
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-01-23
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency Topology Master-slave Pipeline processing Design methodology Clocks Sparse matrices Space exploration Simulated annealing Encoding
Content Type	Text
Resource Type	Article

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