NDLI: A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces

Content Provider	IEEE Xplore Digital Library
Author	Yu-Hao Hsu Min-Sheng Kao Hou-Cheng Tzeng Ching-Te Chiu Jen-Ming Wu Shuo-Hung Hsu
Copyright Year	2007
Abstract	For the first time, we implemented a reconfigurable load-balanced TDM switch IC with SERDES interface circuits for high speed networking applications. An N times N TDM switch could be constructed recursively from the TDM switch IC to achieve switching capacity of hundred gigabits per second or higher. The TDM switch IC contained a digital 8 times 8 TDM switch core with 8B10B CODECs and analog SERDES I/O interfaces. In the I/O interfaces, eight 2.56/3.2Gbps dual-mode 16/20:1 SERDES with CML buffers were developed. The 16/20:1 instead of 8/10:1 serializer and deserializer were used to reduce the required operating frequency in the switch core by half. New half-rate architectures and all static CMOS gates were used in the 16/20:1 serializer and deserializer for the low power consumption. A wide-band CML I/O buffer with our patented PMOS active load scheme was developed. All implementation were based on the 0.18 mum CMOS technology. Our implementation showed a 20 Gbps switching capacity for the 8 times 8 TDM switch IC.
Starting Page	102
Ending Page	103
File Size	2698302
Page Count	2
File Format	PDF
ISBN	1424406293
DOI	10.1109/ASPDAC.2007.357961
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-01-23
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switches Time division multiplexing CMOS technology Switching circuits Application specific integrated circuits High speed integrated circuits High-speed networks Analog integrated circuits Digital integrated circuits Codecs
Content Type	Text
Resource Type	Article

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