NDLI: A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications

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Model Based Layout Pattern Dependent Metal Filling Algorithm for Improved Chip Surface Uniformity in the Copper Process

Fast and Accurate OPC for Standard-Cell Layouts

Coupling-aware Dummy Metal Insertion for Lithography

Fast Buffer Insertion for Yield Optimization Under Process Variations

A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield

Control-Flow Aware Communication and Conflict Analysis of Parallel Processes

Software Performance Estimation in MPSoC Design

Effective OpenMP Implementation and Translation For Multiprocessor System-On-Chip without Using OS

Creating Explicit Communication in SoC Models Using Interactive Re-Coding

System Architecture for Software Peripherals

A New Boundary Element Method for Multiple-Frequency Parameter Extraction of Lossy Substrates

Hierarchical Optimization Methodology for Wideband Low Noise Amplifiers

PLLSim - An Ultra Fast Bang-Bang Phase Locked Loop Simulation Tool

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Reconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self Compensation

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Improving Execution Speed of FPGA using Dynamically Reconfigurable Technique

Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes

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Configurable AMBA On-Chip Real-Time Signal Tracer

Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic

A Multi-Drop Transmission-Line Interconnect in Si LSI

A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology

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A 0.35um CMOS 1,632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI

Low-Power High-Speed 180-nm CMOS Clock Drivers

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FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control

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ECO-system: Embracing the Change in Placement

Bisection Based Placement for the X Architecture

Slack-based Bus Arbitration Scheme for Soft Real-time Constrained Embedded Systems

A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses

Communication Architecture Synthesis of Cascaded Bus Matrix

Topology exploration for energy efficient intra-tile communication

Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms

Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation

A Graph Reduction Approach to Symbolic Circuit Analysis

Robust Analog Circuit Sizing Using Ellipsoid Method and Affine Arithmetic

WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design

Structured Placement with Topological Regularity Evaluation

Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM

DFM reality in sub-nanometer IC design

DFM/DFY practices during physical designs for timing, signal integrity, and power

Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability

A Novel Performance-Driven Topology Design Algorithm

FastRoute 2.0: A High-quality and Efficient Global Router

DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm

A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction

A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks

LEAF: A System Level Leakage-Aware Floorplanner for SoCs

Protocol Transducer Synthesis using Divide and Conquer approach

A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units

Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture

Architectural Optimizations for Text to Speech Synthesis in Embedded Systems

Deeper Bound in BMC by Combining Constant Propagation and Abstraction

Efficient BMC for Multi-Clock Systems with Clocked Specifications

Symbolic Model Checking of Analog/Mixed-Signal Circuits

Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation

Model-based Programming Environment of Embedded Software for MPSoC

RTOS and Codesign Toolkit for Multiprocessor Systems-on-Chip

Energy-Efficient Real-Time Task Scheduling in Multiprocessor DVS Systems

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Passive Interconnect Macromodeling Via Balanced Truncation of Linear Systems in Descriptor Form

Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods

Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos

Reduced-Order Wide-Band Interconnect Model Realization using Filter-Based Spline Interpolation

Frequency Selective Model Order Reduction via Spectral Zero Projection

Abstract, Multifaceted Modeling of Embedded Processors for System Level Design

Flexible and Executable Hardware/Software Interface Modeling for Multiprocessor SoC Design Using SystemC

A Retargetable Software Timing Analyzer Using Architecture Description Language

Automating Logic Rectification by Approximate SPFDs

BddCut: Towards Scalable Symbolic Cut Enumeration

Node Mergers in the Presence of Don't Cares

Synthesis of Reversible Sequential Elements

Recognition of Fanout-free Functions

Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologies

Challenges to Accuracy for the Design of Deep-Submicron RF-CMOS Circuits

Advanced tools for simulation and design of oscillators/PLLs

A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects

Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion

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Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method

Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-State Analysis of Nonlinear System with Process Variations

Retiming for Synchronous Data Flow Graphs

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MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip

A Run-Time Memory Protection Methodology

Short-Circuit Compiler Transformation: Optimizing Conditional Blocks

Optimization of Arithmetic Datapaths with Finite Word-Length Operands

Exploiting Power-Area Tradeoffs in Behavioural Synthesis through clock and operations throughput selection

A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications

High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs

Numerical Function Generators Using Edge-Valued Binary Decision Diagrams

Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains

An Efficient Computation of Statistically Critical Sequential Paths Under Retiming

Fast Electrical Correction Using Resizing and Buffering

SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design

Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies

Flow-Through-Queue based Power Management for Gigabit Ethernet Controller

Approximation Algorithm for Process Mapping on Network Processor Architectures

Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Architecture

VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond

A High-Throughput Low-Power AES Cipher for Network Applications

Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands

Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space

An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization

Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation

Safe Delay Optimization for Physical Synthesis

Overview on Low Power SoC Design Technology

Development of Low-power and Real-time VC-1/H.264/MPEG-4 Video Processing Hardware

Development of Low Power ISDB-T One-Segment Decoder by Mobile Multi-Media Engine SoC (S1G)

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Logic and Layout Aware Voltage Island Generation for Low Power Design

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Fast Buffered Delay Estimation Considering Process Variations

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Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks

Fast Placement Optimization of Power Supply Pads

Efficient Second-Order Iterative Methods for IR Drop Analysis in Power Grid

A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms

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Fault Dictionary Size Reduction for Million-Gate Large Circuits

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Flow Time Minimization under Energy Constraints

Integrating Power Management into Distributed Real-time Systems at Very Low Implementation Cost

A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation

Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency

CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time

Design Methodology for 2.4GHz Dual-Core Microprocessor

An Embedded Low Power/Cost 16-Bit Data/Instruction Microprocessor Compatible with ARM7 Software Tools

A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications

Exploration of Low Power Adders for a SIMD Data Path

Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning

Multithreaded SAT Solving

Trace Compaction using SAT-based Reachability Analysis

Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets

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A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications

Content Provider	IEEE Xplore Digital Library
Author	Zhenyu Liu Arslan, T. Erdogan, A.T.
Copyright Year	2007
Description	Author affiliation: Sch. of Eng. & Electron., Edinburgh Univ. (Zhenyu Liu; Arslan, T.; Erdogan, A.T.)
Abstract	The use of reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such cores are being used for their flexibility, powerful functionality and low power consumption. Distributed arithmetic (DA) is a powerful algorithm widely used in many fields of multimedia for its efficiency. This paper presents a novel reconfigurable adder-based architecture for DA to realize the inner product which is the key computation in many digital signal processing applications. 1D DCT is mapped onto the architecture. Compared with some existing ASIC designs, the new architecture achieves good performance in area, speed and power.
Starting Page	908
Ending Page	913
File Size	8038006
Page Count	6
File Format	PDF
ISBN	1424406293
DOI	10.1109/ASPDAC.2007.358105
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-01-23
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Arithmetic Computer architecture Discrete cosine transforms Signal processing algorithms Discrete Fourier transforms Read only memory Hardware Design engineering Power engineering and energy Electronic mail
Content Type	Text
Resource Type	Article

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