NDLI: Simulation-based work load and job release control for semiconductor manufacturing

Content Provider	IEEE Xplore Digital Library
Author	Urayama, Keiichiro Fu, Michael C. Marcus, Steven I.
Copyright Year	2015
Description	Author affiliation: Corporate Manufacturing Engineering Center, Toshiba Corporation, Yokohama, Japan (Urayama, Keiichiro) \|\| Department of Electrical and Computer Engineering and Institute for Systems Research, University of Maryland, College Park, 20742, USA (Marcus, Steven I.) \|\| Robert H Smith School of Business and Institute for Systems Research, University of Maryland, College Park, 20742, USA (Fu, Michael C.)
Abstract	Cycle time and capacity management are two of the most important issues for manufacturing companies, particularly in a dynamic business environment. The goal is to meet customer delivery dates while minimizing manufacturing cost. Semiconductor manufacturing involves a large number of process steps, reentrant process flows and long production cycle times. In addition, technological innovation in the semiconductor industry is rapid, resulting in shorter product life cycles. Thus, semiconductor manufacturing companies must continually invest in order to keep pace with new technology and update their equipment to produce new products. These conditions make cycle time and capacity management more important for semiconductor manufacturing companies. For the purpose of stable control of cycle time and capacity, there have been many studies dealing with semiconductor manufacturing shop floor control. This paper focuses on job release control, which aims to keep the work load stable and meet customer delivery dates in the presence of dynamic demand fluctuations. We introduce a hierarchical control model which consists of two layers: a long-term capacity decision model and a short-term job release control model. Parameters of the proposed linear programming (LP) models are estimated using simulation, which acts as an intermediate layer between the two layers. Numerical experiments on a mini-fab demonstrate the potential gains from using our model, which achieves improved customer delivery and shorter cycle time relative to several conventional job release policies.
Starting Page	7329
Ending Page	7334
File Size	320455
Page Count	6
File Format	PDF
e-ISBN	9781479978861
DOI	10.1109/CDC.2015.7403376
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-12-15
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Capacity planning Load modeling Manufacturing Companies Semiconductor device modeling Numerical models
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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