NDLI: Reticle floorplanning with guaranteed yield for multi-project wafers

Content Provider	IEEE Xplore Digital Library
Author	Kahng, A.B. Reda, S.
Copyright Year	2004
Description	Author affiliation: CSE Dept., California Univ., San Diego, La Jolla, CA, USA (Kahng, A.B.; Reda, S.)
Abstract	With the dramatic increase in mask costs, multi-project wafers have became an attractive choice for low-volume chip fabrication. By using the same set of masks to fabricate a number of different chips, the mask-set cost is amortized among different chip providers, leading to significant cost reduction especially for chip prototyping. In this paper, we present a new algorithm for reticle floorplanning with wafer yield guarantees. The previous approach of Kahng et al. considers optimizing both the reticle area and the wafer yield, leading to suboptimal solutions with no yield bounds. By contrast, we consider the yield as a constraint and optimize the area accordingly. We characterize yield constraints and provide a mechanism through which yield can be incorporated into an optimal-area packer. The incorporation of yield constraints prunes large parts of the search space of the optimal-area packer, leading to runtime-efficient optimal-area floorplans with guaranteed yields. Empirical results demonstrate that our approach dominates previous results, i.e., we give floorplans that consume less area and have higher die yields. For the 10 benchmarks, we achieve a yield improvement of 14% with an area reduction of 2%.
Sponsorship	IEEE Comput. Soc. IEEE Circuits and Syst. Soc
Starting Page	106
Ending Page	110
File Size	311747
Page Count	5
File Format	PDF
ISBN	0769522319
ISSN	10636404
DOI	10.1109/ICCD.2004.1347908
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Manufacturing Prototypes Constraint optimization Chip scale packaging Optical design Optical design techniques Optical device fabrication Sawing Production
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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