NDLI: An automatic test pattern generation framework for combinational threshold logic networks

Content Provider	IEEE Xplore Digital Library
Author	Gupta, P. Rui Zhang Jha, N.K.
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. Eng., Princeton Univ., NJ, USA (Gupta, P.; Rui Zhang; Jha, N.K.)
Abstract	We propose an automatic test pattern generation (ATPG) framework for combinational threshold networks. The motivation behind this work lies in the fact that many emerging nanotechnologies, such as resonant tunneling diodes (RTDs) and quantum cellular automata (QCA), implement threshold logic. Consequently, there is a need to develop an ATPG methodology for this type of logic. We have built the first automatic test pattern generator and fault simulator for threshold logic, which has been integrated on top of an existing computer-aided design (CAD) tool. These exploit new fault collapsing techniques we have developed for threshold networks. We perform fault modeling to show that many cuts and shorts in RTD-based threshold gates are equivalent to stuck-at faults at the inputs and output of the gate. Experimental results with the MCNC benchmarks indicate that test vectors were found for all testable stuck-at faults in their threshold network implementations.
Sponsorship	IEEE Comput. Soc. IEEE Circuits and Syst. Soc
Starting Page	540
Ending Page	543
File Size	292242
Page Count	4
File Format	PDF
ISBN	0769522319
ISSN	10636404
DOI	10.1109/ICCD.2004.1347974
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automatic test pattern generation Automatic logic units Logic testing Quantum cellular automata Design automation Resonant tunneling devices Diodes Test pattern generators Computational modeling Computer simulation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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