NDLI: A general post-processing approach to leakage current reduction in SRAM-based FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Lach, J. Brandon, J. Skadron, K.
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Virginia Univ., Charlottesville, VA, USA (Lach, J.; Brandon, J.)
Abstract	A negative effect of ever-shrinking supply and threshold voltages is the larger percentage of total power consumption that comes from leakage current. Several techniques have been developed to help reduce leakage in SRAM-based memory, in which the percent leakage power is especially acute. SRAM-based field programmable gate arrays (FPGAs) pose similar leakage problems, but their structure and function require different solutions. This paper introduces a low complexity post-processing approach to reducing FPGA leakage current by ground-gating off SRAM cells that are unused in a particular device configuration. The approach is general enough to apply to any device configuration, and results reveal that the significant leakage current reduction can be achieved with no delay penalty and acceptable area overhead.
Sponsorship	IEEE Comput. Soc. IEEE Circuits and Syst. Soc
Starting Page	144
Ending Page	150
File Size	292353
Page Count	7
File Format	PDF
ISBN	0769522319
ISSN	10636404
DOI	10.1109/ICCD.2004.1347914
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Leakage current Field programmable gate arrays Energy consumption Random access memory Circuits Threshold voltage CMOS technology Logic devices Cache memory Routing
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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