NDLI: Floorplanning Multiple Reticles for Multi-project Wafers

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Table of contents

New Strategies for System Level Design

DFM in Perspective - A Challenge and Opportunity in Nanometer Era -

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Chaos In Phase Locked Loop

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Floorplanning Multiple Reticles for Multi-project Wafers

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2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT).

Floorplanning Multiple Reticles for Multi-project Wafers

Content Provider	IEEE Xplore Digital Library
Author	Meng-Chiou Wu Shr-Cheng Tsai Rung-Bin Lin
Copyright Year	2006
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Chung-li (Meng-Chiou Wu; Shr-Cheng Tsai; Rung-Bin Lin)
Abstract	Floorplanning chips in more than one reticle for multi-project wafers has not been investigated. In this paper, we propose two approaches to this problem. We first formulate this problem with preselected reticle sizes as a mixed-integer linear programming (MILP) model. We then propose a compatibility-driven B*-tree dissection search (CBTDS) heuristic for it. Experiments for floorplanning chips in two reticles show that the MILP model is too complex to render good results, while CBTDS is very effective and efficient. Compared to a naive solution, CBTDS obtains a floorplan that uses 37% fewer wafers
Starting Page	1
Ending Page	4
File Size	3672694
Page Count	4
File Format	PDF
ISBN	1424401798
DOI	10.1109/VDAT.2006.258145
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-04-26
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor device modeling Production Linear programming Hydrogen Computer science Chip scale packaging Costs Semiconductor device measurement Blades Design methodology
Content Type	Text
Resource Type	Article

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