NDLI: Design and implementation of scalable low-power Montgomery multiplier

Content Provider	IEEE Xplore Digital Library
Author	Hee-Kwan Son Sang-Geun Oh
Copyright Year	2004
Description	Author affiliation: Multimedia Lab., Samsung Electron. Co., South Korea (Hee-Kwan Son; Sang-Geun Oh)
Abstract	In this paper, an efficient Montgomery multiplier is introduced for the modular exponentiation operation, which is fundamental to numerous public-key cryptosystems. Four aspects are considered: performance, power, reliability, and scalability. To increase performance, the architecture is based on the radix-4 carry-save adder (CSA). To lower power consumption, we devised several effective techniques for reducing the spurious transitions and the expected switching activity (ESA) of high fan-out signals. To achieve scalability, we implement a 4-fold nested loop for the whole data processing flow. It is compatible with the multiple-precision digit-serial arithmetic as well as the data transfer to/from an external memory. Finally, to make sure that the arithmetic operation runs correctly without inducing data overflow error, we find out the optimum numbers of bits for all vectors appearing in the operation through a mathematical analysis and a logic simulation. In the evaluation of hardware implemented using 0.18 /spl mu/m CMOS standard library and 4 metal layers, area and current consumption are 59 K gates and 0.4 mA/MHz at 1.8 V supply voltage, respectively. The presented low power techniques save more than 20% of power consumed.
Sponsorship	IEEE Comput. Soc. IEEE Circuits and Syst. Soc
Starting Page	524
Ending Page	531
File Size	377677
Page Count	8
File Format	PDF
ISBN	0769522319
ISSN	10636404
DOI	10.1109/ICCD.2004.1347972
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Scalability Arithmetic Public key cryptography Energy consumption Data processing Error correction Mathematical analysis CMOS logic circuits Analytical models Hardware
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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