NDLI: Gate sizing and V/sub t/ assignment for active-mode leakage power reduction

Content Provider	IEEE Xplore Digital Library
Author	Feng Gao Hayes, J.P.
Copyright Year	2004
Description	Author affiliation: Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA (Feng Gao; Hayes, J.P.)
Abstract	Leakage current is a key factor in IC power consumption even in the active operating mode. We investigate the simultaneous optimization of gate size and threshold voltage to reduce leakage power. We assume a standard-cell-based design flow where the available cell sizes and threshold voltages (V/sub t/'s) are given, and model the optimization as a mixed-integer linear programming (MLP) problem. In addition to the exact model, two faster approximate MLP models are proposed, along with CAD tools that generate the models automatically. We present experimental results which show that optimal designs derived from the exact MLP model can achieve the same performance as all-low-V/sub t/ unit-size designs, but with only one third the leakage power. The approximate MLP models can be solved about 25 times faster than the optimal model with negligible errors. All the proposed models can be extended to take dynamic power and multiple supply voltages into consideration.
Sponsorship	IEEE Comput. Soc. IEEE Circuits and Syst. Soc
Starting Page	258
Ending Page	264
File Size	321288
Page Count	7
File Format	PDF
ISBN	0769522319
ISSN	10636404
DOI	10.1109/ICCD.2004.1347931
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Threshold voltage Energy consumption Delay Leakage current Linear programming Dynamic voltage scaling Design optimization Design automation Power supplies Circuits
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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