NDLI: Asynchronous scan-latch controller for low area overhead DFT

Content Provider	IEEE Xplore Digital Library
Author	Tsukisaka, M. Imai, M. Nanya, T.
Copyright Year	2004
Description	Author affiliation: Res. Center for Adv. Sci. & Technol., Tokyo Univ., Japan (Tsukisaka, M.; Imai, M.; Nanya, T.)
Abstract	This paper introduces a new scan control technique to realize low area overhead of scan-latches. Single transparent-latch is popularly used for register of high-throughput datapaths. For the scan-test of those kind of circuits, each transparent-latch is replaced with scan-latch. Conventional scan-latch cells controlled by synchronous signals consist of L1 latch and additional L2 latch, both of which function as master latch and slave latch respectively in scan mode. Apparently, additional L2 latch may result in area overhead. In order to avoid the area impact of such an additional L2 latch, we propose new timing methodology employing asynchronous control technique asP* protocol, and introduce asynchronous controlled scan-paths whose scan-latch employs only L1 latch. We evaluate the operation speed with HSPICE simulations and see they are practical. We also suggest DFT structure with our suggested asynchronous scan-paths, which is suitable for conventional synchronous test systems.
Sponsorship	IEEE Comput. Soc. IEEE Circuits and Syst. Soc
Starting Page	66
Ending Page	71
File Size	418082
Page Count	6
File Format	PDF
ISBN	0769522319
ISSN	10636404
DOI	10.1109/ICCD.2004.1347901
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Latches Shift registers Circuit testing Timing Master-slave Clocks Application specific processors Protocols Circuit simulation Design for testability
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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