NDLI: Linear programming based techniques for synthesis of network-on-chip architectures

Content Provider	IEEE Xplore Digital Library
Author	Srinivasan, K. Chatha, K.S. Konjevod, G.
Copyright Year	2004
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Arizona State Univ., Tempe, AZ, USA (Srinivasan, K.; Chatha, K.S.; Konjevod, G.)
Abstract	Network-on-chip (NoC) has been proposed as a solution for the communication challenges of system-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity for incorporating custom NoC architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. This paper presents novel linear programming based techniques for synthesis of custom NoC architectures. In the nanoscale regime, low power consumption would continue to be an important design goal. We first discuss an optimal mixed integer linear programming (MILP) formulation that synthesizes a low power NoC architecture subject to the performance constraints. The MILP formulation is limited by large run times. We next present heuristic techniques that exploit clustering, and 0-1 constraint relaxation to reduce the run times of the formulation. The techniques minimize power as the primary goal, and minimize the number of routers (area) as a secondary goal. We present an analysis of the quality of the results and the solution times of the proposed techniques by extensive experimentation with the realistic benchmarks. The clustering based heuristic generates results whose power consumption is within 11% of the MILP solutions and its average run time is 171.1 seconds. The average run time of the relaxation and rounding based techniques is less than 2 seconds, and the power consumption of their solutions is within 58% of the MILP result.
Sponsorship	IEEE Comput. Soc. IEEE Circuits and Syst. Soc
Starting Page	422
Ending Page	429
File Size	698879
Page Count	8
File Format	PDF
ISBN	0769522319
ISSN	10636404
DOI	10.1109/ICCD.2004.1347957
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Linear programming Network synthesis Network-on-a-chip Computer architecture Energy consumption Network topology Bandwidth Application software Delay Routing
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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