NDLI: Structural and Electrical Properties of Ferroelectric-Gate Field-Effect-Transistors Using Au/(Bi,La)4Ti3O12/SrTa2O6/Si Structures

Content Provider	IEEE Xplore Digital Library
Author	Ho-Seung Jeon Jeong-Hwan Kim Joo-Nam Kim Kwang-Hun Park Byung-Eun Park
Copyright Year	2007
Abstract	We fabricated the ferroelectric-gate field effect transistors (Fe-FETs) using a metal-ferroelectric-insulator-semiconductor (MFIS) structure as a gate configuration using $(Bi,La)_{4}Ti_{3}O_{12}$ (BLT) and $SrTa_{2}O_{6}$ (STA) thin films. From the capacitance-voltage (C-V) measurements for MFIS capacitors, a hysteric shift with a clockwise direction was observed and the memory window width was about 1.5 V for the plusmn5 V bias sweep. The leakage current density was as low as $1x10^{-7}$ $A/cm^{2}$ at 5 V. From drain current-gate voltage characteristics of the fabricated Fe-FETs, the obtained threshold voltage shift (memory window) of the device was about 0.5 V due to the ferroelectric nature of BLT film. The drain current-drain voltage characteristics of the fabricated FeFETs showed typical n-channel FETs characteristics.
Starting Page	65
Ending Page	68
File Size	2897078
Page Count	4
File Format	PDF
ISBN	9781424413331
ISSN	10994734
DOI	10.1109/ISAF.2007.4393169
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-05-27
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Gold FETs Capacitance-voltage characteristics Threshold voltage Thin film transistors Capacitance measurement Capacitors Clocks Leakage current Ferroelectric materials
Content Type	Text
Resource Type	Article

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