NDLI: Key Integration Technologies for Nanoscale FRAMs

Content Provider	IEEE Xplore Digital Library
Author	Jung, D.J. Hong, Y.K. Kim, H.H. Park, J.H. Kim, H.S. Kang, S.K. Kim, J.H. Ahn, W.S. Choi, D.Y. Jung, J.Y. Jung, W.W. Lee, E.S. Goh, H.K. Kim, S.Y. Kang, J.Y. Kang, Y.M. Joo, S.H. Lee, S.W.Y. Jeong, H.S. Kinam Kim
Copyright Year	2007
Description	Author affiliation: Samsung Electron. Co. LTD., Yongin (Jung, D.J.; Hong, Y.K.; Kim, H.H.; Park, J.H.; Kim, H.S.; Kang, S.K.; Kim, J.H.; Ahn, W.S.; Choi, D.Y.; Jung, J.Y.; Jung, W.W.; Lee, E.S.; Goh, H.K.; Kim, S.Y.; Kang, J.Y.; Kang, Y.M.; Joo, S.H.; Lee, S.W.Y.; Jeong, H.S.; Kinam Kim)
Abstract	We discuss key technologies of 180 nm-node ferroelectric memories, whose process integration is becoming extremely complex when device dimension shrinks into a nano-scale. This is because process technology in ferroelectric integration does not extend to conventional shrink technology due to many difficulties of coping with MIM (metal-insulator-metal) capacitors. The key integration technologies in ferroelectric random access memory (FRAM) comprise (1) etching technology to have less plasma damage; (2) stack technology for the preparation of robust ferroelectrics; (3) capping technology to encapsulate cell capacitors; and (4) vertical conjunction technology to connect cell capacitors to the plate-line. What has been achieved from these novel approaches is not only to have a peak-to-peak value of 675 mV in bit-line potential but to ensure sensing margin of 300 mV in opposite-state retention even after 1000 hours at 150degC.
Starting Page	19
Ending Page	22
File Size	4072611
Page Count	4
File Format	PDF
ISBN	9781424413331
ISSN	10994734
DOI	10.1109/ISAF.2007.4393154
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-05-27
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Ferroelectric films Nonvolatile memory Ferroelectric materials MIM capacitors Nanoscale devices Metal-insulator structures Etching Plasma applications Plasma devices
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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