NDLI: On hybrid memory allocation for FPGA behavioral synthesis (abstract only)

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On hybrid memory allocation for FPGA behavioral synthesis (abstract only)

Content Provider	ACM Digital Library
Author	Zhang, Qian Ma, Chenfei Xu, Qiang
Abstract	FPGA behavioral synthesis has gained significant momentum recently with the growing interests in accelerating high-performance computing applications. While the latest generation of high-level synthesis (HLS) tools has made significant progress, they still lack the support for certain high-level language features such as dynamic memory allocation, despite the fact that efficiently utilization of the on-chip memory resources in FPGAs is critical to achieve the performance and power consumption target for many designs. To tackle the above problem, in this paper, we propose a novel hybrid memory allocation scheme to map malloc/free in C programing language onto FPGA platforms. By estimating the memory usage and available FPGA memory resources, the scheme judiciously allocates static memory blocks and/or instantiate hardware allocators for memory requests. And the partition between these two parts is based on estimated access counts and solving an ILP to minimize overhead from dynamic memory allocation. Experimental results on benchmark circuits demonstrate the efficacy of the proposed technique.
Starting Page	245
Ending Page	245
Page Count	1
ISBN	9781450326711
DOI	10.1145/2554688.2554697
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-02-26
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Dynamic memory allocation High-level synthesis Fpga
Content Type	Text
Resource Type	Article

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