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Routing Wire Optimization through Generic Synthesis on FPGA Carry Chains - eScholarship
| Content Provider | Semantic Scholar |
|---|---|
| Author | Parandeh-Afshar, Hadi Zgheib, Grace Brisk, Philip Ienne, Paolo |
| Copyright Year | 2011 |
| Abstract | FPGA logic clusters are comprised of look-up tables (LUTs) and arithmetic carry-chains, which perform specific arithmetic operations such as addition. In this paper, we present a generic logic synthesis technique to utilize such dedicated resources by restructuring the already mapped FPGA cicuits. The basic idea is to replace the interconnection wires between the blocks that are logically in a chain by the carry chains, which are hardwired connections. This reduces the pressure on the routing resources and minimizes the utilization of routing wires. We observed that, on average, more than 70% of logic nodes can be restructured and 39% of them form the logic chains that are mappable to the carry chains. Our synthesis approach comprises a fast and memory efficient Boolean matching technique for identifying restructurable nodes and a chaining heuristic to identify the logic chains. This approach can be used effectively in modern high performance FPGA families from both Altera and Xilinx. Our experiments indicate that, on average, 9% of routing wires are saved using this technique. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www1.cs.ucr.edu/faculty/philip/papers/workshops-posters/iwls11/iwls11-carry_chain.pdf |
| Alternate Webpage(s) | http://lap.epfl.ch/files/content/sites/lap/files/shared/publications/ParandehAfsharJun11_RoutingWireOptimizationThroughGenericSynthesisOnFpgaCarryChains_IWLS11.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
