NDLI: Adjacency criticality: a simple yet effective metric for statistical timing yield optimisation of digital integrated circuits

Content Provider	IET Digital Library
Author	Ebrahimipour, Seyed Milad Ghavami, Behnam Raji, Mohsen
Abstract	As CMOS devices become smaller, process variations-induced uncertainty imposes a large spread in the circuit timing and therefore, it becomes one of the main issues for circuit yield. To analyse/optimise the timing of the circuit under process variation effects, statistical analysis/optimisation techniques are more suitable than the traditional static analysis/optimisation counterparts. Statistical gate sizing is an effective technique that is widely used to guide the timing yield improvement of digital circuits. Gate criticality, defined as the probability that a gate lies on a critical path, forms the basis for many of the existing statistical gate sizing techniques. Here, the authors introduce adjacency criticality to address the drawbacks of the conventional definition of gate criticality. It is defined as the probability of manufacturing a chip in which the gate lies on the critical path due to process variation considering the effect of the gates in its fan-out cone. Furthermore, the authors present the levelised Adjacency Criticality metric which provides a trade-off between the runtime of the criticality metric and accuracy of the Adjacency Criticality metric. In order to show the efficacy of the proposed metric, an adjacency criticality-based statistical gate sizing method is presented for improving timing yield of the circuit.
Starting Page	979
Ending Page	987
Page Count	9
ISSN	1751858X
Volume Number	13
e-ISSN	17518598
Issue Number	Issue 7, Oct (2019)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/13/7
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.5616
Journal	IET Circuits, Devices & Systems
Publisher Date	2019-05-13
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	AC-based Statistical Gate Sizing Method Adjacency Criticality Circuit Timing Circuit Yield CMOS Device CMOS Digital Integrated Circuit CMOS Integrated Circuit Critical Path Digital Circuit Digital Circuit Design, Modelling And Testing Digital Integrated Circuit Gate Criticality Levelised AC Metric Optimisation Optimisation Technique Process Variation Effect Statistical Analysis Statistical Gate-sizing Technique Statistical Timing Yield Optimisation Statistics Timing Circuit Variation-induced Uncertainty
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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