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Content Provider | IEEE Xplore Digital Library |
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Author | Herndon, W.H. |
Copyright Year | 1989 |
Description | Author affiliation: Integraph Corp., Palo Alto, CA, USA (Herndon, W.H.) |
Abstract | A comparison of the high-performance static random access memories (SRAMs) of today to those of 20 years ago (1969) shows that the performance has been increased by a factor of 10 while costs have been improved by a factor of 100. An overview of SRAM circuits is provided, covering early configurations; ECL memory cells; alpha-particle soft errors; cross-coupled SCR cells; I/sup 2/L (or MTL); BiCMOS and CMOS RAMs with ECL I/O: and cache-size requirements for high-performance systems. It is seen that the consistent evolutionary path has been to maximize performance by minimizing the power dissipation in the inactive portion of the circuit. High-performance computing systems require cache/main-memory combinations capable of matching processor speed. In these systems, the delay of the interconnect communicating with the cache is a significant portion of the total cycle time.< |
Starting Page | 203 |
Ending Page | 208 |
File Size | 482141 |
Page Count | 6 |
File Format | |
DOI | 10.1109/BIPOL.1989.69492 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 1989-09-18 |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | SRAM chips Random access memory Costs Thyristors BiCMOS integrated circuits CMOS memory circuits Power dissipation Delay systems Delay effects Integrated circuit interconnections |
Content Type | Text |
Resource Type | Article |
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