NDLI: Statistical security analysis of AES with X-tolerant response compactor against all types of test infrastructure attacks with/without novel unified countermeasure

Content Provider	IET Digital Library
Author	Popat, Jayesh Mehta, Usha
Abstract	Advanced encryption standard (AES) crypto-algorithm design can be implemented in software and hardware. No known attacks are available that can break the AES with brute force or cryptanalysis in finite time. However, when the AES is implemented in hardware, test infrastructure such as scan chain, stimuli decompressor, response compactor and built-in self-test (BIST) are included in the normal design for making the crypto-chip easily testable after manufacturing. This test infrastructure is highly susceptible to attacks. The attacker may misuse the scan-chain content for the retrieval of secret key from AES hardware. In this study, the authors investigated scan-chain attack based on different distributions of key-related flip-flops of AES hardware implementation with X-tolerant response compactor-based test infrastructure. The modular exponentiation security scheme as a counter measure against test infrastructure attacks is proposed. In this study, the statistical security analyses are performed with and without the proposed countermeasure in case of AES hardware followed by X-tolerant test response compactor. The experimental result shows that the proposed countermeasure thwarts the attack with almost constant rate for different distributions of key-related flops in the scan-chain, and hence it is not dependent on the nature of scan-chain architecture design.
Starting Page	1117
Ending Page	1124
Page Count	8
ISSN	1751858X
Volume Number	13
e-ISSN	17518598
Issue Number	Issue 8, Nov (2019)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/13/8
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2019.0083
Journal	IET Circuits, Devices & Systems
Publisher Date	2019-06-25
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Advanced Encryption Standard Crypto-algorithm Design AES Hardware Implementation Brute Force Counter Measure Cryptanalysis Crypto-chip Cryptography Digital Circuit Design, Modelling And Testing Finite Time Flip Flops Logic And Switching Circuit Logic Circuit Logic Testing Modular Exponentiation Security Scheme Novel Unified Countermeasure Scan Chain Scan-chain Architecture Design Scan-chain Attack Scan-chain Content Secret Key Retrieval Statistical Analysis Statistical Security Analysis Test Infrastructure Attack X-tolerant Response Compactor-based Test Infrastructure X-tolerant Test Response Compactor
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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