NDLI: Architecture-aware routability-driven placer for large-scale mixed-size designs

Content Provider	IET Digital Library
Author	Datta, Prasun Mukherjee, Shyamapada
Abstract	In this study, the authors have presented a simple but robust routability-driven placement for the mixed-size designs. The proposed technique is implemented through (i) look-ahead legalisation-based global placement, (ii) congestion removal and (iii) detailed placement stages. A balanced clustering technique has been proposed to group the circuit blocks into clusters based on the types of circuit blocks and their connectivity. A 0-1 integer programming-based global placement method is framed, which performs look-ahead legalisation. A new site information table concept is introduced to keep the information about each placement cell. Based on the divide conquer strategy, placement area is divided into a region to reduce problem size. A force-directed method has been conceived to select an appropriate region for global placement for the blocks of a cluster. A new congestion removal approach substitutes the legalisation stage to remove circuit block congestion and pin density in different regions. Finally, a gain-based strategy has been introduced for routability-driven detailed placement. The proposed technique is implemented and tested on ICCAD 2012 benchmark circuits. It achieves 1.92 and 0.13% improvements in terms of half perimeter wirelength and routing congestion w.r.t. recent placers.
Starting Page	1209
Ending Page	1220
Page Count	12
ISSN	1751858X
Volume Number	13
e-ISSN	17518598
Issue Number	Issue 8, Nov (2019)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/13/8
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.5518
Journal	IET Circuits, Devices & Systems
Publisher Date	2019-08-07
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Architecture-aware Routability-driven Placer Balanced Clustering Technique Circuit Block Congestion Circuit Block Congestion Removal Circuit Optimisation Congestion Removal Approach Digital Circuit Design, Modelling And Testing Divide And Conquer Method Divide Conquer Strategy Force-directed Method Gain-based Strategy Global Placement Half Perimeter Wirelength ICCAD 2012 Benchmark Circuit Integer Programming Integrated Circuit Layout Large-scale Mixed-size Designs Layout Look-ahead Legalisation Modelling And Testing Network Routing Optimisation Technique Pin Density Placement Cell Routability-driven Detailed Placement Routability-driven Placement Routing Congestion Semiconductor Integrated Circuit Design Site Information Table
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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