NDLI: Design impacts of delay invariant high-speed clock delayed dual keeper domino circuit

Content Provider	IET Digital Library
Author	Angeline, A. Anita Bhaaskaran, V. S. Kanchana
Abstract	Precise keeper control of domino logic circuit can significantly increase the speed of operation. However, the positive feedback gain associated with the feedback keeper circuit unduly increases the delay variability. Here, a novel high-speed clock delayed dual keeper (CDDK) domino circuit is presented, which aims at reducing the delay and lower the impact of loop gain on delay variability. In CDDK domino structure, the keeper circuit comprising of two keeper devices is disabled during the initial evaluation phase. This significantly reduces the contention current and thereby the operating speed of the circuit is enhanced. The simulations of the circuits have been carried out for various metrics and the results have been analysed. Furthermore, the Monte–Carlo simulations carried out for 2000 runs on a 128-input OR gate using CDDK structure demonstrate reduced delay variability characteristics due to smaller loop gain of the CDDK domino structure against the conventional domino logic style. The enhanced speed of operation due to reduced contention current is demonstrated. The results are validated through comparison against the conventional domino logic counterpart circuits. The analyses of the circuits are performed using industry standard full-suite Cadence® tools using 90 nm technology library.
Starting Page	1134
Ending Page	1141
Page Count	8
ISSN	1751858X
Volume Number	13
e-ISSN	17518598
Issue Number	Issue 8, Nov (2019)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/13/8
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.5410
Journal	IET Circuits, Devices & Systems
Publisher Date	2019-07-12
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	CDDK Domino Structure CDDK Structure Clock And Data Recovery Circuit CMOS Digital Integrated Circuit CMOS Logic Circuit Conventional Domino Logic Counterpart Circuit Conventional Domino Logic Style Delay Delay Invariant High-speed Clock Delay Variability Delay Variability Characteristic Design Impacts Digital Circuit Design, Modelling And Testing Domino Logic Circuit Dual Keeper Domino Circuit Feedback Feedback Keeper Circuit Initial Evaluation Phase Integrated Circuit Design Keeper Circuit Comprising Keeper Device Logic And Switching Circuit Logic Circuit Logic Design Method Logic Element Logic Gate Low Power Electronics Monte Carlo Method Monte–Carlo Simulations Novel High-speed Clock Operating Speed Positive Feedback Gain Precise Keeper Control Reduced Contention Current Size 90 Nm Smaller Loop Gain
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Skew-Tolerant Domino Circuits (1997)

High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits

Domino logic.

A high-speed circuit design for power reduction & evaluation contention minimization in wide fan-in OR gates

Domino Logic with Variable Threshold Voltage Keeper (2003)

A Double Capacitive Body Biased Circuit for High Performance Domino Logic with CMOS Keeper

Noise measurement in high-speed domino pseudo-CMOS keeper

Speed and Noise Immunity Enhanced Low Power Dynamic Circuits

Clock Delayed Domino Logic With Efficient Variable Threshold Voltage Keeper

Design impacts of delay invariant high-speed clock delayed dual keeper domino circuit

Similar Documents

Skew-Tolerant Domino Circuits (1997)

High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits

Domino logic.

A high-speed circuit design for power reduction & evaluation contention minimization in wide fan-in OR gates

Domino Logic with Variable Threshold Voltage Keeper (2003)

A Double Capacitive Body Biased Circuit for High Performance Domino Logic with CMOS Keeper

Noise measurement in high-speed domino pseudo-CMOS keeper

Speed and Noise Immunity Enhanced Low Power Dynamic Circuits

Clock Delayed Domino Logic With Efficient Variable Threshold Voltage Keeper

Design impacts of delay invariant high-speed clock delayed dual keeper domino circuit