NDLI: DECO: DIMM controller efficient for ECC operations

Content Provider	IET Digital Library
Author	Jang, Wooyoung
Abstract	An error-correcting code (ECC) immune to bit errors can make memory performance severely degraded since incomplete-word ECC write requests lead to inefficient operations on a dual in-line memory module (DIMM). A DIMM controller efficient for such ECC operations is proposed. The key idea is that read-to-write and write-to-read operations caused by incomplete-word ECC write requests are split into independent read and write operations, and then the read and write operations are individually scheduled under data coherence constraints. Experimental results show that the proposed DIMM controller achieves 11% shorter memory latency, and 9.3% higher memory utilisation, on average, than the latest conventional DIMM controller in industrial multimedia applications. Moreover, it achieves up to 2.1 times higher memory performance on synthetic benchmarks.
Starting Page	1349
Ending Page	1351
Page Count	3
ISSN	00135194
Volume Number	50
e-ISSN	1350911X
Issue Number	Issue 19, Sep (2014)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/50/19
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2014.1135
Journal	Electronics Letters
Publisher Date	2014-09-01
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Code Data Coherence Constraint DECO DIMM Controller ECC Operations Error Correction Code Error-correcting Code Integrated Memory Circuit Memory Circuit Memory Latency Memory Utilisation Read-to-write Operation Semiconductor Storage Write-to-read Operation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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