NDLI: Lower complexity error location detection block of adjacent error correcting decoder for SRAMs

Content Provider	IET Digital Library
Author	Maity, Raj Kumar Tripathi, Sayan Samanta, Jagannath Bhaumik, Jaydeb
Abstract	Multiple cell upsets (MCUs) caused by radiation is an important issue related to the reliability of embedded static random access memories (SRAMs). Multiple random and adjacent error correcting codes have been extensively employed for several years to protect stored data in SRAMs against MCUs. A compact and fast error correcting codec is desirable in most of these applications. In this study, simplified expressions for error location detection (ELD) block for single error correction-double error detection-double adjacent error correction (SEC-DED-DAEC) and single error correction-double error detection-triple adjacent error correction (SEC-DED-TAEC) decoders have been obtained by employing Karnaugh map. The conventional SEC-DED-DAEC and SEC-DED-TAEC decoders have been designed and implemented in both field-programmable gate array and ASIC platforms by considering these simplified ELD expressions. In FPGA platform, the proposed design for SEC-DED-DAEC and SEC-DED-TAEC decoders require 1.37–28.40% improvement in area and maximum 14.74% improvement in delay compared to existing designs. Whereas ASIC-based designs provide 2.20–26.81% reduction in area and 0.30–28.96% reduction in delay compared to existing related works. So the proposed design can be considered as an efficient alternative of traditional adjacent error correcting decoders in resource constraint applications.
Starting Page	210
Ending Page	216
Page Count	7
ISSN	17518601
Volume Number	14
e-ISSN	1751861X
Issue Number	Issue 5, Sep (2020)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cdt/14/5
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2019.0268
Journal	IET Computers & Digital Techniques
Publisher Date	2020-04-28
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Adjacent Error Correcting Codes Adjacent Error Correcting Decoder Application Specific Integrated Circuit ASIC Platforms Code Conventional SEC-DED-DAEC Decoding Error Correcting Codec Error Correction Code Error Correction-double Error Detection Error Detection Code Error Location Detection Block Field Programmable Gate Array Field-programmable Gate Array Karnaugh Map Logic And Switching Circuit Logic Circuit Memory Circuit Multiple Cell Upsets Multiple Random Error Correcting Code Resource Constraint Application SEC-DED-TAEC Decoders Semiconductor Storage SRAM SRAM Chips Static Random Access Memories Triple Adjacent Error Correction
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Software

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