NDLI: 500 V SOI lateral pin diode with dual deep-oxide trenches for fast reverse recovery and suppressed oscillation

Content Provider	IET Digital Library
Author	Zhu, Jing Zhang, Long Sun, Weifeng Huang, Keqin Du, Yicheng
Abstract	A 500 V silicon-on-insulator (SOI) lateral pin diode is proposed. The proposed structure features dual deep-oxide trenches (DDOTs) arranged in the i-layer. In off-state, the dual DDOTs can help to sustain the potential between the cathode and the anode. With the breakdown voltage of 500 V level, the i-layer length of the proposed structure can be dramatically shortened compared with the conventional SOI diode. The fast reverse recovery is obtained due to the reduced amount of the stored carrier in on-state. During the reverse recovery, the holes can be trapped by the gap between the adjacent deep-oxide trenches (DOTs). Therefore, dynamic punch-through is avoided and suppressed oscillation can be realised. The proposed structure achieves a reverse recovery time of 72 ns which is an improvement by 28% compared with the conventional SOI diode. Meanwhile, the waveform oscillation of the proposed structure is successfully suppressed, which is superior to the normal DOTs SOI lateral pin diode.
Starting Page	71
Ending Page	73
Page Count	3
ISSN	00135194
Volume Number	52
e-ISSN	1350911X
Issue Number	Issue 1, Jan (2016)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/52/1
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2015.1879
Journal	Electronics Letters
Publisher Date	2015-11-17
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Breakdown Voltage Dual Deep-oxide Trenches Dynamic Punch-through Electric Breakdown Fast Reverse Recovery I-layer Length Junction And Barrier Diode Oscillation P-i-n Diode Silicon-on-insulator SOI Lateral PiN Diode Suppressed Oscillation Time 72 Ns Voltage 500 V Waveform Oscillation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Reverse-recovery of diamond p-i-n diodes

500 V dual gate deep-oxide trench SOI-LIGBT with improved short-circuit immunity

Design for EMI suppression during reverse recovery by 600V lateral SOI PiN diode with traps

Design and optimization of a novel SOI LDMOS structure using PIN junction

Simulation of Electrical Characterization on Lateral Silicon-on-Insulator PIN Diode for Space Radiation Detector

High Voltage and Fast Switching Reverse Recovery Characteristics of 4H-SiC PiN Diode

High-voltage superjunction VDMOS with low reverse recovery loss

Simulation study of high-reverse blocking AlGaN/GaN power rectifier with an integrated lateral composite buffer diode

Lateral bipolar transistor on partial SOI: A 2D simulation study

500 V SOI lateral pin diode with dual deep-oxide trenches for fast reverse recovery and suppressed oscillation

Similar Documents

Reverse-recovery of diamond p-i-n diodes

500 V dual gate deep-oxide trench SOI-LIGBT with improved short-circuit immunity

Design for EMI suppression during reverse recovery by 600V lateral SOI PiN diode with traps

Design and optimization of a novel SOI LDMOS structure using PIN junction

Simulation of Electrical Characterization on Lateral Silicon-on-Insulator PIN Diode for Space Radiation Detector

High Voltage and Fast Switching Reverse Recovery Characteristics of 4H-SiC PiN Diode

High-voltage superjunction VDMOS with low reverse recovery loss

Simulation study of high-reverse blocking AlGaN/GaN power rectifier with an integrated lateral composite buffer diode

Lateral bipolar transistor on partial SOI: A 2D simulation study

500 V SOI lateral pin diode with dual deep-oxide trenches for fast reverse recovery and suppressed oscillation