NDLI: Digital excess loop delay compensation technique with embedded truncator for continuous-time delta

Content Provider	IET Digital Library
Author	He, Tao Zhang, Yi Temes, Gabor C.
Abstract	A novel implementation is proposed to relax the specifications of the internal feedback path for a continuous-time delta–sigma modulator. A truncator is embedded into the digital excess loop delay (ELD) compensation path. Thermometer-coded truncation is achieved by re-ordering the reference voltages of the internal quantiser. This requires only a small amount of extra digital circuitry compared to the conventional digital ELD compensation. The digital encoder controlling the digital-to-analogue converter is simple, and it only introduces a small ELD.
Starting Page	20
Ending Page	21
Page Count	2
ISSN	00135194
Volume Number	52
e-ISSN	1350911X
Issue Number	Issue 1, Jan (2016)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/52/1
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2015.1595
Journal	Electronics Letters
Publisher Date	2015-11-17
Access Restriction	Open
Rights Holder	© Crown Copyright
Subject Keyword	A/D And D/A Convertor Continuous-time Delta-sigma Modulators Delta-sigma Modulation Digital Circuit Digital Encoder Digital Excess Loop Delay Compensation Digital-to-analogue Converter Embedded Truncator Extra Digital Circuitry Internal Feedback Path Internal Quantiser Power Electronics Power Supply Reference Circuit Reference Voltage Supervisory Circuit Thermometer-coded Truncation Thermometers
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Digital excess loop delay compensation for high speed delta–sigma modulators

Time-shifted excess loop delay compensation DAC for 2-T s delay in CT-ΔΣ ADCs

Efficient technique for excess loop delay compensation in continuous-time ΔΣ modulators

Compensation method of the excess loop delay in continuous-time delta-sigma analog-to-digital converters based on model matching approach

A Comparative Study on Excess-Loop-Delay Compensation Techniques for Continuous-Time Sigma–Delta Modulators

Excess Loop Delay Compensation in Continuous-Time Delta-Sigma Modulators

High-loop-delay sixth-order bandpass continuous-time sigma–delta modulators

A Continuous-Time $Delta Sigma$ ADC Utilizing Time Information for Two Cycles of Excess Loop Delay Compensation

A 0.89-mW 1-MHz 62-dB SNDR Continuous-Time Delta–Sigma Modulator With an Asynchronous Sequential Quantizer and Digital Excess-Loop-Delay Compensation

Digital excess loop delay compensation technique with embedded truncator for continuous-time delta–sigma modulators

Similar Documents

Digital excess loop delay compensation for high speed delta–sigma modulators

Time-shifted excess loop delay compensation DAC for 2-T s delay in CT-ΔΣ ADCs

Efficient technique for excess loop delay compensation in continuous-time ΔΣ modulators

Compensation method of the excess loop delay in continuous-time delta-sigma analog-to-digital converters based on model matching approach

A Comparative Study on Excess-Loop-Delay Compensation Techniques for Continuous-Time Sigma–Delta Modulators

Excess Loop Delay Compensation in Continuous-Time Delta-Sigma Modulators

High-loop-delay sixth-order bandpass continuous-time sigma–delta modulators

A Continuous-Time $Delta Sigma$ ADC Utilizing Time Information for Two Cycles of Excess Loop Delay Compensation

A 0.89-mW 1-MHz 62-dB SNDR Continuous-Time Delta–Sigma Modulator With an Asynchronous Sequential Quantizer and Digital Excess-Loop-Delay Compensation

Digital excess loop delay compensation technique with embedded truncator for continuous-time delta–sigma modulators