NDLI: Reliable majority voter based on spin transfer torque magnetic tunnel junction device

Content Provider	IET Digital Library
Author	Butzen, P. F. Slimani, M. Wang, Y. Cai, H. Naviner, L. A. B.
Abstract	A reliable majority voter circuit using a nanometre spin transfer torque magnetic tunnel junction (STT-MTJ) is presented. The circuit tolerates single transient faults and manages process variations due to technology downscaling. The use of this magnetic device brings non-volatility memory to logic circuits and promises to overcome the rising standby power issue. By using the STMicroelectronics fully depleted silicon on insulator 28 nm design kit and a precise STT-MTJ compact model, electrical simulations have been carried out to show its low-power and high reliability performances.
Starting Page	47
Ending Page	49
Page Count	3
ISSN	00135194
Volume Number	52
e-ISSN	1350911X
Issue Number	Issue 1, Jan (2016)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/52/1
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2015.2738
Journal	Electronics Letters
Publisher Date	2015-11-12
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Fully Depleted Silicon on Insulator Integrated Circuit Reliability Logic And Switching Circuit Logic Circuit Magnetic Device Magnetic Tunnelling Magneto-acoustic Wave Device Magnetoresistive Wave Device Magnetostrictive And Magnetostatic Wave Device Majority Voter Circuit Reliability Mathematical Analysis MRAM Device Nonvolatility Memory Process Variation Reliability Silicon-on-insulator Size 28 Nm Spin Transfer Torque Magnetic Tunnel Junction STMicroelectronics Storage Application STT-MTJ Technology Downscaling Torque Transient Analysis Transient Fault
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Realization of spin-torque transfer magnetoresistive RAM

High performance MRAM-based stateful logic

Two-transistor and two-magnetic-tunnel-junction multi-level cell structured spin-transfer torque magnetic random access memory with optimisations on power and reliability

Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing

Ultra-energy-efficient CMOS/magnetic non-volatile flip-flop based on spin-orbit torque device

A Survey on Circuit Modeling of Spin-Transfer-Torque Magnetic Tunnel Junctions

Conditioning Circuits for Nanoscale Perpendicular Spin Transfer Torque Magnetic Tunnel Junctions as Magnetic Sensors

Self-adjusting sensing circuit without speed penalty for reliable STT-MRAM

Variation-Tolerant Sensing Circuit for Spin-Transfer Torque MRAM

Reliable majority voter based on spin transfer torque magnetic tunnel junction device

Similar Documents

Realization of spin-torque transfer magnetoresistive RAM

High performance MRAM-based stateful logic

Two-transistor and two-magnetic-tunnel-junction multi-level cell structured spin-transfer torque magnetic random access memory with optimisations on power and reliability

Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing

Ultra-energy-efficient CMOS/magnetic non-volatile flip-flop based on spin-orbit torque device

A Survey on Circuit Modeling of Spin-Transfer-Torque Magnetic Tunnel Junctions

Conditioning Circuits for Nanoscale Perpendicular Spin Transfer Torque Magnetic Tunnel Junctions as Magnetic Sensors

Self-adjusting sensing circuit without speed penalty for reliable STT-MRAM

Variation-Tolerant Sensing Circuit for Spin-Transfer Torque MRAM

Reliable majority voter based on spin transfer torque magnetic tunnel junction device