NDLI: FPGA implementation of a high-speed, real-time, windowed standard deviation filter

Content Provider	IET Digital Library
Author	Herbert, J. Wilson, S. Rakic, A. D. Taimre, T.
Abstract	Characterisation of the standard deviation of a time-series signal has uncommon, yet widespread applications. The usual requirement for a representation of signal standard deviation in real-time implies a high computation speed. A method based on a field programmable gate array (FPGA) implementation is presented. The technique is benchmarked against conventional computational approaches and shows a single windowed standard deviation update calculation of a 16 bit sample can be achieved in 11 ns on a modern CPU. The FPGA implementation is found to be superior to all other approaches examined with an operation time of below 10 ns, and thus provides a useful tool for the real-time measurement of the standard deviation of signals above 100 MHz.
Starting Page	22
Ending Page	23
Page Count	2
ISSN	00135194
Volume Number	52
e-ISSN	1350911X
Issue Number	Issue 1, Jan (2016)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/52/1
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2015.2407
Journal	Electronics Letters
Publisher Date	2015-11-27
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Field Programmable Gate Array Filter Filter And Other Network FPGA Logic And Switching Circuit Logic Circuit Modern CPU Statistics Time Series Time-series Signal Windowed Standard Deviation Filter Word Length 16 Bit
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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