NDLI: Process enabling highly accurate die position for fan-out package applications

Content Provider	IET Digital Library
Author	Park, H. P. Kim, Y. H.
Abstract	A new process that can improve die shift issue in process utilising back-sided under bump metallurgy (UBM) via a self-alignment effect for fan-out package applications is proposed. The die and the pad of the substrate are spontaneously aligned and the degree of accuracy is very high after reflow. For the experiment, two kinds of UBM pads were prepared on glass dies and the SAC305 solder was formed on the copper pads of an frame retardent (FR)-based substrate. The die shift value was from 20 to 50 μm after pick-and-placement. After reflow, the maximum die shift value was <1 μm. An initially misaligned die with a large shift was aligned with a high degree of accuracy during reflow due to the surface tension of the molten solder. The proposed process improves the die shift issue in the fabrication of fan-out wafer-level packaging and the active die embedded substrate.
Starting Page	810
Ending Page	812
Page Count	3
ISSN	00135194
Volume Number	53
e-ISSN	1350911X
Issue Number	Issue 12, Jun (2017)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/53/12
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2017.0357
Journal	Electronics Letters
Publisher Date	2017-05-11
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Active Die Embedded Substrate Back-sided under Bump Metallurgy Copper Pads Die Shift Issue Die Shift Value Fan Out Wafer Level Packaging Fan-out Package Application FR-4-based Substrate Glass Dies Position Control Process Enabling Highly Accurate Die Position Product Packaging SAC305 Solder Self-alignment Effect Semiconductor Integrated Circuit UBM Pads Wafer Level Packaging
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Development of advanced fan-out wafer level package (embedded Wafer Level BGA) packaging

Investigation of Warpage for Multi-Die Fan-Out Wafer-Level Packaging Process

Die-to-package coupling extraction for fan-out wafer-level-packaging

Advance semiconductor package applied on high efficiency dual-mode DC-DC buck converter

Mean time to failure in wafer level-csp packages with snpb and snagcu solder bumps.

Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging

Shear performance and accelerated reliability of solder interconnects for fan-out wafer-level package

Fan-out WLP — The enabler for system-in-package on Wafer Level (WLSIP)

Influence of under-bump metallurgy and solder alloys on the crack in the wafer level chip scale packaging

Process enabling highly accurate die position for fan-out package applications

Similar Documents

Development of advanced fan-out wafer level package (embedded Wafer Level BGA) packaging

Investigation of Warpage for Multi-Die Fan-Out Wafer-Level Packaging Process

Die-to-package coupling extraction for fan-out wafer-level-packaging

Advance semiconductor package applied on high efficiency dual-mode DC-DC buck converter

Mean time to failure in wafer level-csp packages with snpb and snagcu solder bumps.

Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging

Shear performance and accelerated reliability of solder interconnects for fan-out wafer-level package

Fan-out WLP — The enabler for system-in-package on Wafer Level (WLSIP)

Influence of under-bump metallurgy and solder alloys on the crack in the wafer level chip scale packaging

Process enabling highly accurate die position for fan-out package applications