NDLI: Acceleration of Generalized Minimum Aberration Designs of Hadamard Matrices on Graphics Processing Units

Content Provider	IEEE Xplore Digital Library
Author	Calhoun, J. Graham, J. Hong Zhou Hai Jiang
Copyright Year	2012
Abstract	The process of applying generalized minimum aberration criteria (GMAC) to non-regular fractional factorial designs is extremely computationally intensive. Constructing and ranking all designs can take hours if not days; therefore, exploitation of the massively parallel nature of modern graphics processing units (GPUs) are used to perform the task. The computation is not just ported to the GPU, but is implemented as to optimize performance based upon the modern GPU architecture. Optimizations include using bit operations and table lookups to reduce the number of addition and multiplication operations performed. Tables are housed in GPU constant memory with almost no latency for access. Using a statistical proof from previous research reduces the memory required for the calculation. Optimizations regarding memory storage and transfer in NVIDIA's Compute Unified Device Architecture (CUDA) are also explored, as well as advance features such as streams and multiple GPUs. Experimental results have demonstrated the effectiveness of the proposed approach.
Starting Page	1294
Ending Page	1300
File Size	625563
Page Count	7
File Format	PDF
ISBN	9781467321648
DOI	10.1109/HPCC.2012.191
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-25
Publisher Place	United Kingdom
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Generalized Minimum Aberration Criteria Hadamard Matrices Compute Unified Device Architecture Memory management Error correction Error correction codes Graphics Processing Unit Indexes Kernel Graphics processing unit Sorting
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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