NDLI: Fully Distributed On-chip Instruction Memory Design for Stream Architecture Based on Field-Divided VLIW Compression

Content Provider	IEEE Xplore Digital Library
Author	Yi He Maolin Guan Chunyuan Zhang Tian Tian Qianming Yang
Copyright Year	2012
Abstract	Huge code size and poor code density have always been a serious problem in VLIW processor. In order to deal with the problem and its influence on the instruction memory in stream architecture, this paper proposes a novel method called field-divided VLIW compression through analyzing the code characteristics of stream program across a wide range of typical stream application domains and dividing the instruction code unrelated to each other into different subfields. Based on the field-divided VLIW compression, this paper designs a fully distributed on-chip instruction memory (FDIM) for stream architecture. The experiment on MASA stream processor demonstrates that the field-divided VLIW compression can reduce about 38% of off-chip instruction code and about 66% of on-chip instruction memory space demand in the case of having little influence on the program performance; FDIM reduces the area of on-chip instruction memory by about 37%, thus reduces the area of the MASA stream processor by about 8.92%. Besides, the energy consumption of instruction memory is decreased by about 61%.
Starting Page	25
Ending Page	32
File Size	957687
Page Count	8
File Format	PDF
ISBN	9781467321648
DOI	10.1109/HPCC.2012.14
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-25
Publisher Place	United Kingdom
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	field-divided VLIW compression code characteristics analysis Memory management stream architecture fully distributed instruction memory Streaming media Registers VLIW System-on-a-chip Kernel
Content Type	Text
Resource Type	Article

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