NDLI: Implementation and Evaluation of Large Interconnection Routers for Future Many-core Networks on Chip

Content Provider	IEEE Xplore Digital Library
Author	Zaytoun, A.H.M. Fahmy, H.A.H. Elsayed, K.M.F.
Copyright Year	2012
Abstract	As the number of processing elements in the future Networks on Chip (NoC) increases from multi-cores to many-cores, the role of the interconnection communications becomes more critical. The number of cores on a System on Chip (SoC) will reach thousands in the near future as predicted by the International Technology Roadmap for Semiconductors (ITRS). Currently, NoC interconnections are mostly implemented with m×n 2-D mesh topology connecting small size routers. This will represent the bottleneck to the communication latency for the increasing number of cores where the average number of hops the data have to pass will increase. In this paper, we propose an alternative NoC interconnecting scheme by using large routers interconnecting large number of cores in star topology. This interconnection scheme can be scaled up by using hierarchical-star or fat-tree topologies. We present the implementation and performance evaluation of three large router architectures and compare their efficiency to the small 5×5 router used in the mesh topology. We develop a simulating environment that resembles the real NoC conditions to test the routers throughput and average latency on different buffer sizes and under different traffic loads. We also synthesize them to estimate the area and power consumption. Then, routers efficiencies are calculated with respect to the area and power consumption.
Starting Page	524
Ending Page	531
File Size	552983
Page Count	8
File Format	PDF
ISBN	9781467321648
DOI	10.1109/HPCC.2012.77
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-25
Publisher Place	United Kingdom
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Networks-on-chip (NoC) Network topology Microprocessors Computer architecture Switches System-on-chip (SoC) Crossbar Topology Delay Batcher-Banyan
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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