NDLI: An Implementation of Parallel 1-D FFT on the K Computer

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An Implementation of Parallel 1-D FFT on the K Computer

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An Implementation of Parallel 1-D FFT on the K Computer

Content Provider	IEEE Xplore Digital Library
Author	Takahashi, D. Uno, A. Yokokawa, M.
Copyright Year	2012
Abstract	In this paper, we propose an implementation of a parallel one-dimensional fast Fourier transform (FFT) on the K computer. The proposed algorithm is based on the six-step FFT algorithm, which can be altered into the recursive six-step FFT algorithm to reduce the number of cache misses. The recursive six-step FFT algorithm improves performance by utilizing the cache memory effectively. We use the recursive six-step FFT algorithm to implement the parallel one-dimensional FFT algorithm. The performance results of one-dimensional FFTs on the K computer are reported. We successfully achieved a performance of over 18 TFlops on 8192 nodes of the K computer (82944 nodes, 128 GFlops/node, 10.6 PFlops peak performance) for a 2^41-point FFT.
Starting Page	344
Ending Page	350
File Size	197691
Page Count	7
File Format	PDF
ISBN	9781467321648
DOI	10.1109/HPCC.2012.53
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-25
Publisher Place	United Kingdom
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computers Distributed databases all-to-all communication Fast Fourier transform distributed-memory parallel computer Registers Arrays Indexes Kernel Equations
Content Type	Text
Resource Type	Article

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