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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kuei-Chung Chang Ing-Ming Liao Bo-Yi Shiu |
| Copyright Year | 2010 |
| Description | Author affiliation: Department of Information Engineering and Computer, Science, Feng-Chia University, Taiwan (Kuei-Chung Chang; Ing-Ming Liao; Bo-Yi Shiu) |
| Abstract | As technology scaling enables the integration of billions of transistors on a chip, economies of scale are prompting the move toward parallel chip architectures with application-specific systems-on-a-chip (SoC) leveraging multiple cores on a single chip for better performance at manageable design costs. The demand for communicating capability of many-core SoC will definitely increase because the traffic flow between cores, memory, and cache will be massive and complicated. As these parallel chip architectures scale in size, on-chip networks (NoC) have become the main communication architecture, replacing dedicated interconnections and shared buses. These NoCs have been adopted to mitigate wire delay in specific domains such as Nonuniform Cache Architectures (NUCA). The paper presents a NoC design which provides priority-based communications coordinating with wormhole-switching as well as XY routing algorithm. In the proposed NoC, the important packets will be transmitted first with the higher priority to save the waiting time. The experimental results show the proposed priority-based NoC can increase the transmission efficiency in NUCA for many-core SoCs. |
| Starting Page | 483 |
| Ending Page | 488 |
| File Size | 480490 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424476398 |
| e-ISBN | 9781424476404 |
| DOI | 10.1109/COMPSYM.2010.5685465 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-12-16 |
| Publisher Place | Taiwan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | On-chip interconnection Protocols Nonuniform cache architecture Computer architecture Switches Channel allocation Many-core systems Routing System-on-a-chip Resource management |
| Content Type | Text |
| Resource Type | Article |
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