NDLI: An equivalent circuit model for high-k/metal gate stack MOS capacitor with dynamic leakage

Content Provider	IEEE Xplore Digital Library
Author	Chang-Woo Sohn Eui-Young Jeong Hyun Chul Sagong Do-Young Choi Min Sang Park Chang Yong Kang Jinyong Chung Yoon-Ha Jeong
Copyright Year	2010
Description	Author affiliation: Department of Electronic and Electrical Engineering, Pohang University of Science and Technology, Pohang 790-784, Korea (Chang-Woo Sohn; Eui-Young Jeong; Hyun Chul Sagong; Do-Young Choi; Min Sang Park; Yoon-Ha Jeong) \|\| College of Information Technology and Engineering, Inha University, Incheon 402-751, Korea (Jinyong Chung) \|\| SEMATECH, 2706 Motopolis Drive, Austin, TX 78741, USA (Chang Yong Kang)
Abstract	This paper presents a simple equivalent circuit model to characterize a gate impedance of MOS capacitor with high-k dielectric, which exhibited significant dynamic leakage. Series of RC-shunts was added to consider the effects of charge trapping in high-k dielectric. From our model, it is found that two-frequency method using the megahertz range gives us reasonable values for the gate capacitance because the traps with large time constants are unable to response the modulating frequency. Also, parameters for our model are systematically analyzed.
Starting Page	291
Ending Page	294
File Size	335459
Page Count	4
File Format	PDF
ISBN	9781424488964
e-ISBN	9781424488971
DOI	10.1109/NMDC.2010.5651924
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage measurement MOS capacitors Logic gates Capacitance Dielectrics Frequency measurement Integrated circuit modeling
Content Type	Text
Resource Type	Article

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