NDLI: Fundamental Research of No-Flow UF for Low Stress Flip-Chip Package

Content Provider	IEEE Xplore Digital Library
Author	Kawamoto, S. Suzuki, O. Abe, Y. Yoshii, H. Fujiki, T. Tanaka, F.
Copyright Year	2005
Description	Author affiliation: NAMICS Corp., Niigata (Kawamoto, S.; Suzuki, O.; Abe, Y.; Yoshii, H.; Fujiki, T.; Tanaka, F.)
Abstract	Recently, most of semiconductor companies are developing high density packages using lead free solder and low-k layer. The melting temperature of lead free solder is higher than the eutectic solder. Therefore, the reflow profile for lead free solder is higher approximately 30 degrees C than the conventional profile. When a high temperature profile is used, the organic substrate is expanded and the package stress becomes higher. Furthermore, bump cracking by the package stress is concerned, because lead free solder is very fragile. In addition, it is easy to destroy the low-k layer by the package stress such as the package's warpage. Thus the stress control is necessary for the assembly process of high density packages using lead free solder and low-k layer. It is effective to use no-flow underfill (NUF) with local reflow process using a flip chip bonder (FCB). This process can realize an assembly with lower stress compared with capillary flow underfill (CUF) reflow process, because the organic substrate should not be exposed to a high temperature and is controlled not to expand much. NUF characteristics for local reflow process are investigated. At first, NUF curability and the influence of flux-ability for the solder connection were evaluated using NUF which was based on the epoxy resin and different kinds of hardeners. It was confirmed that solder connection was affected by NUF curability and the flux-ability were influenced by the hardener type. Then filler loading level was optimized to reinforce the solder joint. We improved the mismatch between IC chip and substrate in the C.T.E (coefficient of thermal expansion). NUF of various filler contents were evaluated under reliability tests such as moisture reflow test, temperature cycle test, and high temperature/high humidity test. Finally the package stress with a low stress NUF was evaluated by shadow moire technique. As a result, it was confirmed that the package by local reflow process had a lower stress than the package by conventional process
Starting Page	1
Ending Page	5
File Size	827282
Page Count	5
File Format	PDF
ISBN	0780392922
DOI	10.1109/HDP.2005.251388
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-06-27
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Environmentally friendly manufacturing techniques Temperature Testing Substrates Semiconductor device packaging Stress control Assembly Thermal stresses Lead compounds Flip chip
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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