NDLI: Methodology Research & ASIC Design for OLED Scan Driver

Please wait, while we are loading the content...

2007 International Symposium on High Density packaging and Microsystem Integration

Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, 2006. HDP'06.

2005 Conference on High Density Microsystem Design and Packaging and Component Failure Analysis

Digital Memory Card Market and Technology

Experiments on the Bonding Interface Vibration of Thermosonic Flip Chip

Post-bond Compression Process for Bonding Thin-Die on BT Substrate using Thermoplastic Adhesive Tape

Study of Ultrasonic Power Parameter on the Large Aluminum Wire Wedge Bonding Strength

Reliability Study for Test Lands Targeting during Electrical Testing

Switch Design and Implementation for Network-on-Chip

Mechanism Analysis of Process Parameters Effects on Bondability in Ultrasonic Ball Bonding

Key Learning from Quanta ICT Low resistance Failure Issue

The 2004 International Electronics Manufacturing Initiative (iNEMI) Technology Roadmaps

Synchronization Trigger System Design of the Thermosonic Flip-chip Bonding

Sub-100 micron pitch stencil printing for wafer scale bumping

BGA 44um Fine Pitch Low K Wire Bonding Process Development

Mechanics of Interfacial Delamination in IC Packages Undergoing Solder Reflow

Study on the fatigue life of the FC-BGA solder joints with Damage

Elemental Redistribution and Diffusion Path Configuration Near the Edge of Sn-95Pb Solder Bump/Ni-Cu UBM Joints after Aging in the Flip-Chip Technology

Macro-Micro Modeling Analysis for High Density Packaged Flip Chips

Adhesion Study of Copper Layer Deposited onto Liquid Crystalline Polymer for Electronic Packaging

Interface Modelling of ACA Interconnects Using Micropolar Theory

An Ontology for Isotropic Conductive Adhesive Interconnect Technology in Electronics Packaging Applications

Effect of curing conditions on the interconnect properties of isotropic conductive adhesives composed of an epoxy-based binder

Fundamental Research of No-Flow UF for Low Stress Flip-Chip Package

Residual Stress in Flip Chip Joining Using Anisotropic Conductive Adhesive

Test speed dependency of peel strength of ACF joints

High Performance Anistropic Conductive Adhesives for Lead-free Interconnects

Ontology for the anisotropic conductive adhesive interconnect technology for electronics packaging applications

Intermetallic Compound Formation and Diffusion Path Evolution in the Flip Chip Sn-37Pb Solder Bump after Aging

Optimization of lead free solder paste for robust process and reliable solder joint.

The Evaluation of Sn-58Bi Composite Solder Mixed with Y2O3

High Strain Rate Testing of Solder Interconnections

Microstructural evolution of Sn-Zn based lead free solders after temperature and humid atmosphere exposure

Wetting Dynamics Study of Sn-Ag Solder during Reflow

Drop Impact Reliability - A Comprehensive Summary

An Analytical Model for Thermal Stress Analysis of Multi-layered Microelectronic Packaging

Moisture assist delamination in multiple die stacked package

Failure Analysis of Foreign Materials in Electronic Packaging Assembly

Evaluation of Bondability and Reliability of Single Crystal Copper Wire Bonding

Solder Paste Printability Tester

Compressive Load Challenges on Sub 1.00 Ball Pitch for Flip Chip Ball Grid Array (FCBGA)

Thermal and Mechanical Loading Effects on the Reliability of COG-ACF with Thin Glass by FEA

Evaporation of small-molecule nanolayers-growth, structure, electronic levels and devices

The Structure Design and Packaging of The Polarization-maintaining Dual Fiber Collimator based on DFT

Integrated Capacitors and Resistors on Liquid Crystal Polymer Substrate

Newly Developed LCP Film Fabricated by Solvent-Casting Method

Embedded Passive Technology Application: Design and Fabrication of an Automotive Engine Controller

Characterization of Low-Temperature Sintered Nanoscale Silver Paste for Attaching Semiconductor Devices

Nano-machining Experiment of Metal Materials Polishing with Ice Desk

Circuit Tracks on 3-D Thermoplastic Surfaces

Localized Micro-Inserts Connection for Smart Card Secure Micro Packaging

Packaging Issues on Combination of LED and Flip Chip

Increase stability D-Pak package transistors to thermal loadings

The Influence of Nonideal Iso-Heat-Flux Boundary on Impinging Jet Heat Transfer Experimental Results in Modeled High Density Electronics Packaging

Experimental Research on Heat Transfer of Confined Air Jet Impingement with Tiny Size Round Nozzle in High Density Electronics Packaging Model

Estimate of the Power Dissipation of Multilayer and High Density Nano-CMOS Chip

Coffin-Manson Equation determination for Sn-Zn Based Lead-Free Solder Joints

Feasibility Study of a SiP for High Performance and Reliability Product Application

UWB Radio Module Design for Wireless Intelligent Systems-From Specification to Implementation

Numerical Investigation Based on CFD for Air Impingement Heat Transfer in Electronics Cooling

A Nanocore/CMOS Hybrid System-on-Package (SoP) Architecture for Future Nanoelectronic Systems

Interfacial failure Analysis of CdZnTe detectors by Scanning Acoustic Microscopy and Auger Electron Spectrum

Recent Advances on Polymers and Polymer Nanocomposites for Advanced Electronic Packaging Applications

Evolution of Interconnects and Packaging

Impacts of Pb-free legislation on European HDP

Global Trend in Electronics Manufacturing

Design and Fabrication of Micro-Compliant Amplifier with Topology Optimal Compliant Mechanism Integrated with a Piezoelectric Microactuator

Wafer Level Thin Film Encapsulation for MEMS

Optical Measurements for Micro- and Opto-electronic Packages/Substrates

Anamorphic Lens MEMS

Experiment study influences of some process parameters on dispensing dots consistency in contact dispensing process

Underwater Robot Vertical Manipulator Control

Modeling Analysis and Designing the Flight Control System on A Sub-Mini Unmanned Helicopter Robot

Switch Design and Implementation for Network-on-Chip

Vibration Simulation of Transducer System in Thermosonic Wire bonding

Experimental Studies of Frequency Characteristic on Transducer Power Supply and Vibration System in Ultrasonic Bonding System

Analysis and modeling non-Newtonian fluid transferring process and dot formation in contact dispensing

Non-Contact Topography Measurements Due to Thermal Deformation in Bonded Structures

Photolithography on Grossly Non-Planar Substrates

Vacuum Packaging Process Simulation for MEMS Devices

A 0.18 μm CMOS Ultra-Wideband Low-Noise Amplifier with High IIP3

Study on Pitch Deviation for Coupling Loss in Fiber Collimator Packing

Joint Time-Frequency Analysis of Capillary Tip Vibration in Thermosonic Wire Bonding

Atomic Diffusion Properties in Al/Ni & Au/Al Bond Interface

Features of bonded interface and PZT transducer

Design for Manufacturability and Reliability of Embedded Display Smart Card

Study On a Mixed Verification Strategy for IP-Based SoC Design

A New Partitioning Scheme of Parallel VHDL Simulation

A Sub-1-V Linear CMOS Bandgap Voltage Reference

Methodology Research & ASIC Design for OLED Scan Driver

A novel double-T-shaped microstrip resonator and its design for microwave filter

A novel H-shaped microstrip resonator and its design to filter using defected ground structure

A High-Speed Memory Interface Architecture for MPEG2 Video Decoder

A Fourth-Order 18-b Delta-Sigma A/D Converter

The Application of Linear-Quadratic Gaussian Control Theory for Sub-mini Helicopter

IP Core Design of PLC Microprocessor with Boolean Module

DSP-Based Intelligent Tension Controller

An Bidirectional IP Wrapper Design for SoC DFT

A System-level Mixed DFT-TAM Structure For SoC Design

A Fast Group-based Variable-length Decoder and ASIC Implementation

A Novel Digital Signal Interface Design Used in OLED-On-Silicon

Design of 16MB Addressing Spaces in an MCU Based on the MCS-51 Structure

The Study Of Improved RWPA For The Multiple-Core Chip

Proceedings of the Sixth IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis (HDP '04)

Methodology Research & ASIC Design for OLED Scan Driver

Content Provider	IEEE Xplore Digital Library
Author	Ran Feng Xu Mei-hua Chen Zhang-jin Ji Yuan Kang Zhi-ying
Copyright Year	2005
Description	Author affiliation: Microelectron. Res. & Dev. Center, Shanghai Univ. (Ran Feng)
Abstract	The paper first argues the system level design of the OLED drive chip. After analyzing the feature of OLED and the display panel (Sempel and Buchel, 2002), it presents how to eliminate the cross talk effect by the precharge circuit, and compares the drive efficiency between two precharge schemes. Then the dual radix interleaving clock architecture is proposed to enhance the lighting efficiency and dynamic feature of the OLED display panel. The circuit is realized by the dual state machine locks. At last the article demonstrates the effect on the efficiency of both display and transmission between the three RAM management architecture enables the OLED drive chip adapt to different gray scales
Starting Page	1
Ending Page	5
File Size	122323
Page Count	5
File Format	PDF
ISBN	0780392922
DOI	10.1109/HDP.2005.251454
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-06-27
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Application specific integrated circuits Organic light emitting diodes Flat panel displays Clocks Drives Driver circuits Interleaved codes Brightness Digital control Energy management
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in