NDLI: A novel response surface method for design optimization of electronic packages

Content Provider	IEEE Xplore Digital Library
Author	Bo Ping Wang Zhen Xue Han Leon Xu Reinikainen, T.
Copyright Year	2005
Description	Author affiliation: Texas Univ., Arlington, TX, USA (Bo Ping Wang; Zhen Xue Han)
Abstract	The response surface method has been widely used in practical engineering design optimization problems, where the optimal searches are based on the response surfaces mimicking the physical processes or models. Sometimes the response surface method is the only practical option to be able to perform design optimization, such as simulation-based design optimization when the simulations are usually computationally expensive. In conventional approaches, the response surfaces are usually built up using a group of sampling points based on certain design of experiment schemes. The accuracy of the response surface depends largely on the number of sampling points and their distributions in the design space, as well as the approximation functions for the response surface. Currently there is no general method that could achieve the necessary accuracy of a response surface with the minimal expensive (or the number of sampling points). In this paper, a novel sequential response surface updating approach is proposed to improve the efficiency and the accuracy of simulation-based optimizations for electronic packages. It is a dynamic and adaptive approach, which starts with a small number of initial sampling points based on Halton sequence (also called quasi Monte Carlo method), and then refines the response surface by adding more sampling points during the optimization process. This method is demonstrated with a design optimization problem of the thermo-mechanical analyses of a ceramic chip carrier assembly. A simplified thermo-mechanical model is used to perform the interfacial stress analysis of the solder bounding. The objective of is to minimize the interfacial stress by changing the bonding compliance in the specified design space. The case study indicates that, comparing with the conventional direct methods, this approach could greatly improve the computational efficiency of optimization processes with the needed accuracy for simulation-based design optimization.
Sponsorship	IEEE - CPMT
Starting Page	175
Ending Page	181
File Size	1172000
Page Count	7
File Format	PDF
ISBN	0780390628
DOI	10.1109/ESIME.2005.1502795
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-04-18
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Response surface methodology Design optimization Electronics packaging Sampling methods Computational modeling Thermomechanical processes Thermal stresses Design engineering Optimization methods Ceramics
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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