NDLI: Thermal performance and solder joint reliability for board level assembly of modified leadframe package

Content Provider	IEEE Xplore Digital Library
Author	Chien Chen Lee Chang Chun Lee Kou Ning Chiang
Copyright Year	2005
Description	Author affiliation: Dept. of Power Mech. Eng., National Tsing Hua Univ., Hsinchu, Taiwan (Chien Chen Lee; Chang Chun Lee)
Abstract	As we move forward toward the miniaturization of electronic devices, small size, high reliability and good thermal dissipation capability are not only convenient but they are also necessity of the design. However complicated factorial analyses were concurrent with module design, hi this study, a 40-lead modified leadframe "land grid array" (LGA) module mounted on a printed circuit board was investigated. The influences of board level solder joint reliability and thermal dissipation capability were studied and applied with "analysis of variance" (ANOVA). "design of experiments" (DOE) was widely used in factory process improvement, similarly, this study implement the concept of "design of simulation" (DOS) in the beginning design phase. In order to effectively remove the thermal generated from the chip, the thermal via was designed to provide a better thermal performance. The number of thermal via will depend on the package construction, product application and power consumption. Although we know that more the number of thermal via, better the thermal dissipation performance, there is a trend of thermal dissipation capability will become saturated with increasing via number, the increment performance improvement goes down. Through FEM simulation, this curve could be easily found. With regards to cost saving consideration, hollow board design was implemented to provide enough peripheral conducted copper under exposed pad. However, through this hollow design approach, there is a point of diminishing returns as bigger hole size may significantly decrease the thermal performance. This study shows the relationship between hole size and thermal performance. Extend the research to board level solder joint reliability, DOS was implemented to this study. From package structure physical phenomena, we knew that the solder mask type (solder mask define: SMD; and non-solder mask: NSMD) and solder paste thickness were the significant factors in package design. This study adopted 5 main factors with 2 levels each for DOS. Through DOS, we verified the extreme significant factor was solder mask type. This is because of solder extends to the land side surface of NSMD design, more soldering area on land compared with SMD design. Besides, the interaction between solder mask type and solder paste thickness take the third place in accumulative Plato chart.
Sponsorship	IEEE - CPMT
Starting Page	553
Ending Page	558
File Size	1076041
Page Count	6
File Format	PDF
ISBN	0780390628
DOI	10.1109/ESIME.2005.1502866
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-04-18
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Soldering Assembly Lead Electronic packaging thermal management Analysis of variance Printed circuits Thermal factors US Department of Energy Production facilities Analytical models
Content Type	Text
Resource Type	Article

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