NDLI: Thermal modeling for power MOSFETs in DC/DC applications

Content Provider	IEEE Xplore Digital Library
Author	Bulut, Y. Pandya, K.
Copyright Year	2004
Description	Author affiliation: Vishay Siliconix, Inc., Santa Clara, CA, USA (Bulut, Y.; Pandya, K.)
Abstract	In DC-to-DC converters, power MOSFETs in through-hole packages have almost completely disappeared as the industry moves toward all-surface-mount implementations. This means increasing demand for power MOSFET packages with smaller footprint, lower profile, and lower thermal resistance. While MOSFETs in the D/sup 2/PAK and DPAK packages could provide the appropriate level of power dissipation for DC-to-DC applications, their physical size constrained converter-packaging density. Surface-mount alternatives such as the SO-8 address size issues, but their thermal performance is limited by a need to dissipate power through the leads and onto the PCB. One of the principal concerns in DC-to-DC power supply design is controlling heat. By increasing the efficiency of the power switch (MOSFET), it is possible to reduce heat generated, reducing size requirements and need for heat sinking. Optimal power design distributes power across the DC-to-DC converter to eliminate (or at least greatly reduce) hotspots on the power board. To achieve this, it is critical early in the design phase to understand the thermal effects of critical components. The provision of a heat flow model for the MOSFET, accurately predicting temperature effects for the switching elements on the PCB, will save time in development and allow for optimal space utilization and power component distribution. Recent major developments in silicon technology have helped power MOSFET manufacturers to reduce on-resistance (r/sub DS(on)/) for a given die size to almost negligible levels. MOSFETs for switching applications are now available with silicon resistances around 1 m/spl Omega/. Having reached this plateau, attention is being turned to ways that innovative packaging can be used to improve overall device thermal performance. A basic measure of a device's thermal performance is the junction-to-case thermal resistance, R/sub TH,JC/, which is the thermal resistance between a power MOSFET junction and a specified reference point on the device case or package. However, finding the junction temperatures of all the devices on a PCB can be quite difficult, especially for new packages. Without any statistical data or any experience to draw upon, relying only upon the thermal resistance of the device's package from data sheet junction-to-case (R/sub TH,JC/) specifications can produce significant errors. Thus, predicting thermal performance precisely at board level is almost impossible. Many designers are now turning to software simulation techniques to generate representations of a system's thermal performance.
Sponsorship	IEEE-CPMT
Starting Page	429
Ending Page	433
File Size	954328
Page Count	5
File Format	PDF
ISBN	0780384202
DOI	10.1109/ESIME.2004.1304074
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-05-10
Publisher Place	Belgium
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFETs Thermal resistance Packaging DC-DC power converters Heat sinks Space heating Space technology Silicon Power dissipation Surface resistance
Content Type	Text
Resource Type	Article

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