NDLI: True Minimum Energy Design Using Dual Below-Threshold Supply Voltages

Content Provider	IEEE Xplore Digital Library
Author	Kyungseok Kim Agrawal, V.D.
Copyright Year	2011
Abstract	This paper investigates sub threshold voltage operation of digital circuits. The minimum energy per cycle operating point with a single voltage for this mode is known. We further lower the energy per cycle below that point by using dual sub threshold supplies. We call this the true minimum. Special considerations are used in the design for eliminating level converters. We give new mixed integer linear programs (MILP) that automatically and optimally assign gate voltages, avoid the use of level converters, and determine and hold the minimum critical path delay, while minimizing the total energy per cycle. Using examples of a 16-bit ripple-carry adder and a 4 × 4 multiplier we show energy savings of 23% and 5%, respectively. The latter is a worst case example because most paths are critical. Alternatively, for the same energy as that of single below-threshold supply, an optimized dual voltage design can operate at 3 to 4 times higher clock rate. The MILP optimization with special consideration for level converters is general and applicable to any supply voltage range.
Starting Page	292
Ending Page	297
File Size	281963
Page Count	6
File Format	PDF
ISBN	9781612843278
ISSN	10639667
DOI	10.1109/VLSID.2011.67
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-01-02
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Delay Converters Adders CMOS integrated circuits Clocks Integrated circuit modeling
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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