NDLI: Ensuring On-Die Power Supply Robustness in High-Performance Designs

Content Provider	IEEE Xplore Digital Library
Author	Soman, S. Brahme, A. Venkatraman, R. Shaikh, R. Thiyagaraja, S. Patil, M.
Copyright Year	2011
Abstract	VLSI designs in advanced technology nodes increasingly have more power dissipation packed in a smaller area due to high levels of logic integration. Local power demand causes high current to flow through a power distribution network which is normally designed based on average current considerations, while even in normal switching scenarios, the average current is much less than the peak current. The instantaneous flow of high current results in dynamic voltage drops in the power network, which can affect the design performance. In this paper, we discuss methods to ensure power grid robustness by avoiding high dynamic voltage drop issues, and hence improve the overall reliability of the design. The analyses and techniques were adopted on a ~100 sq.mm., 40nm system-on-chip (SoC) design with peak clock frequency of 1.2GHz, and having 10 individual processors along with a collection of hardware accelerators. We also present relevant results highlighting the overall improvements seen.
Starting Page	220
Ending Page	225
File Size	637162
Page Count	6
File Format	PDF
ISBN	9781612843278
ISSN	10639667
DOI	10.1109/VLSID.2011.62
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-01-02
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration design robustness Power grid IR dynamic voltage drop
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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