NDLI: Interconnected Tile Standing Wave Resonant Oscillator Based Clock Distribution Circuits

Content Provider	IEEE Xplore Digital Library
Author	Mandal, A. Karkala, V. Khatri, S.P. Mahapatra, R.N.
Copyright Year	2011
Abstract	Standing wave oscillators (SWOs) are attractive since they can sustain extremely high oscillation frequencies with very low power consumption due to their resonant nature. In this paper, we present a technique to design a high frequency SWO to cover a large area on an IC. We achieve this by combining two techniques. The first technique increases the area coverage of an individual SWO by ensuring that it sustains an odd number (greater than one) of standing waves along the ring. The second approach further increases the area coverage by tiling multiple SWOs side by side, and connecting them such that they oscillate with the same high frequency and phase. The combined approach is simulated for a 3×3 array of tiles, using 3D, skin-effect adjusted RLC parasitic extraction. Our simulations are performed using a 90nm process, and indicate that this tiled structure can oscillate at about 7.25 GHz, with low power (about 68 mW per SWO tile) and low jitter (about 3.1% of the nominal clock period).
Starting Page	82
Ending Page	87
File Size	678755
Page Count	6
File Format	PDF
ISBN	9781612843278
ISSN	10639667
DOI	10.1109/VLSID.2011.70
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-01-02
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Oscillators Inverters Wire Resonant frequency RLC circuits Integrated circuits
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A PLL design based on a standing wave resonant oscillator

Oscillator noise

10GHz clock distribution using coupled standing-wave oscillators

Design of a high-efficiency class DE tuned power oscillator

A 44 GHz Quadrature Traveling Wave Oscillator

Research of transformer based bufferless resonant clock network

Frequency Tolerance Limitations with Logic Gate Clock Oscillators

A 140µA 34ppm/°C 30MHz Clock Oscillator in 28nm CMOS Bulk Process

A High-Frequency Clock Distribution Network Using Inductively Loaded Standing-Wave Oscillators

Interconnected Tile Standing Wave Resonant Oscillator Based Clock Distribution Circuits

Similar Documents

A PLL design based on a standing wave resonant oscillator

Oscillator noise

10GHz clock distribution using coupled standing-wave oscillators

Design of a high-efficiency class DE tuned power oscillator

A 44 GHz Quadrature Traveling Wave Oscillator

Research of transformer based bufferless resonant clock network

Frequency Tolerance Limitations with Logic Gate Clock Oscillators

A 140µA 34ppm/°C 30MHz Clock Oscillator in 28nm CMOS Bulk Process

A High-Frequency Clock Distribution Network Using Inductively Loaded Standing-Wave Oscillators

Interconnected Tile Standing Wave Resonant Oscillator Based Clock Distribution Circuits