NDLI: MEMS-Based Power Gating for Highly Scalable Periodic and Event-Driven Processing

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4×2Gbps Source-Synchronous Transmitter in 45nm CMOS

Self-Calibrating Equalizer for Optimal Jitter Performance Using On-chip Eye Monitoring

A New Double Data Rate(DDR) Dual-Mode Duobinary Transmitter Architecture

An Approach to Tolerate Process Related Variations in Memristor-Based Applications

A SOI EEPROM Based Configuration Cell with Simple Scrubbing Detection

Power Scalable Digital Baseband Architecture for IEEE 802.15.4

Evolution of Oscillation in a Quadrature Oscillator

Quadrature Error Compensation for Jitter Reduction in High Speed Clock and Data Recovery Circuits

A 1.8GHz Digital PLL in 65nm CMOS

Auxiliary State Machines and Auxiliary Functions: Constructs for Extending AMS Assertions

Variation-Conscious Formal Timing Verification in RTL

A Novel Learning Framework for State Space Exploration Based on Search State Extensibility Relation

Improved Timing Windows Overlap Check Using Statistical Timing Analysis

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Interconnected Tile Standing Wave Resonant Oscillator Based Clock Distribution Circuits

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Pseudo Concurrent Quad-Band LNA Operating in 900 MHz/1.8 GHz and 900 MHz/2.4 GHz Bands for Multi-standard Wireless Receiver

Extraction of Aspect Ratio for Non-Manhattan CMOS Devices

A Highly Stable Leakage-Based Silicon Physical Unclonable Functions

Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction

AcENoCs: A Configurable HW/SW Platform for FPGA Accelerated NoC Emulation

A Library Development Framework for a Coarse Grain Reconfigurable Architecture

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Automated Physical Design of Microchip-Based Capillary Electrophoresis Systems

Layout-Aware Solution Preparation for Biochemical Analysis on a Digital Microfluidic Biochip

Dual Code Compression for Embedded Systems

A Scalable LDPC Decoder on GPU

Self-Immunity Technique to Improve Register File Integrity Against Soft Errors

Modeling the Effect of Gate Fringing and Dopant Redistribution on the Inverse Narrow Width Effect of Narrow Channel Shallow Trench Isolated MOSFETs

Development of a Micro-mechanical Logic Inverter for Low Frequency MEMS Sensor Interfacing

Performance Comparison of Thin-Film Transistors Fabricated Using Different Purity Semiconducting Nanotubes

Feedback Based Supply Voltage Control for Temperature Variation Tolerant PUFs

Ensuring On-Die Power Supply Robustness in High-Performance Designs

A Reconfigurable Processor for Phylogenetic Inference

NoC Based Distributed Partitionable Memory System for a Coarse Grain Reconfigurable Architecture

Intra-Flit Skew Reduction for Asynchronous Bypass Channel in NoCs

Low Power Asynchronous Data Acquisition Front End for Wireless Body Sensor Area Network

Hardware Implementation of Real-Time Speech Recognition System Using TMS320C6713 DSP

Improving Android Performance and Energy Efficiency

Hazard-Aware Directed Transition Fault ATPG for Effective Critical Path Test

Fault Collapsing Using a Novel Extensibility Relation

Optimized Multitone Test Stimulus Driven Diagnosis of RF Transceivers Using Model Parameter Estimation

A Robust and Reconfigurable Multi-mode Power Gating Architecture

MEMS-Based Power Gating for Highly Scalable Periodic and Event-Driven Processing

True Minimum Energy Design Using Dual Below-Threshold Supply Voltages

LA-LRU: A Latency-Aware Replacement Policy for Variation Tolerant Caches

Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization

VaROT: Methodology for Variation-Tolerant DSP Hardware Design Using Post-Silicon Truncation of Operand Width

Design of a 20 MHz DC-DC Buck Converter with 84 Percent Efficiency for Portable Applications

Low Offset, Low Noise, Variable Gain Interfacing Circuit with a Novel Scheme for Sensor Sensitivity and Offset Compensation for MEMS Based, Wheatstone Bridge Type, Resistive Smart Sensor

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A General Algorithm for Energy-Aware Dynamic Reconfiguration in Multitasking Systems

Wakeup Time and Wakeup Energy Estimation in Power-Gated Logic Clusters

Trading Accuracy for Power with an Underdesigned Multiplier Architecture

Efficient Trace Signal Selection for Post Silicon Validation and Debug

Trace Buffer-Based Silicon Debug with Lossless Compression

Multiple Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization

Multi-CoDec Configurations for Low Power and High Quality Scan Test

Thermal-Aware Test Scheduling Using On-chip Temperature Sensors

Path Delay Tuning for Performance Gain in the Face of Random Manufacturing Variations

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MEMS-Based Power Gating for Highly Scalable Periodic and Event-Driven Processing

Content Provider	IEEE Xplore Digital Library
Author	Henry, M.B. Lyerly, R. Nazhandali, L. Fruehling, A. Peroulis, D.
Copyright Year	2011
Abstract	For periodic and event-driven applications with long standby times, controlling leakage is essential. This paper investigates using MEMS switches for power gating processors, which eliminates standby leakage power and allows for highly scalable processing. We show that when power gating with a MEMS switch, low technology nodes and low threshold voltages, which offer low switching energy and high speeds, are optimal. We also compare a MEMS-gated processor to two recent low leakage processors and show that it is ideal for applications with 100+ ms standby times. With CMOS compatibility on the horizon, MEMS switches are an attractive option for low-leakage applications.
Starting Page	286
Ending Page	291
File Size	593132
Page Count	6
File Format	PDF
ISBN	9781612843278
ISSN	10639667
DOI	10.1109/VLSID.2011.66
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-01-02
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Program processors Microswitches Micromechanical devices CMOS integrated circuits Threshold voltage Logic gates Contacts
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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