NDLI: AcENoCs: A Configurable HW/SW Platform for FPGA Accelerated NoC Emulation

Content Provider	IEEE Xplore Digital Library
Author	Lotlikar, S. Pai, V. Gratz, P.V.
Copyright Year	2011
Abstract	he heterogeneous nature of the modern day applications has resulted in widespread use of Multicore SoC architectures. The emerging Network-On-Chip (NoC) interconnect architecture provides an energy-efficient and scalable communication solution for multiple cores, serving as a powerful replacement for traditional bus architectures. The key to the successful realization of such architectures is a flexible, fast and robust emulation platform. This paper presents the design, implementation and evaluation of AcENoCs, a flexible and cycle-accurate FPGA emulation platform for validating synchronous and GALS-based NoC architectures. The emulation platform is built around a HWSW framework consisting of reconfigurable network components, traffic generators and ejectors, statistics collection and analysis modules. We also address the unique features of our platform in terms of reconfigurability and co-design of the hardware and software components, and assess the performance improvements and tradeoffs over existing PGA emulators and software simulators. Our experimental analysis indicate speedup improvements in the order of 10000-12000X over HDL simulators and 14-47X over software simulators, without sacrificing cycle accuracy.
Starting Page	147
Ending Page	152
File Size	206505
Page Count	6
File Format	PDF
ISBN	9781612843278
ISSN	10639667
DOI	10.1109/VLSID.2011.46
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-01-02
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Emulation Software Field programmable gate arrays Hardware Registers Synchronization Clocks
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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