NDLI: Exploiting temporal decoupling to accelerate trace-driven NoC emulation

Content Provider	IEEE Xplore Digital Library
Author	Krishnaiah, G. Silpa, B.V.N. Panda, P.R. Kumar, A.
Copyright Year	2011
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Delhi, New Delhi, India (Krishnaiah, G.; Silpa, B.V.N.; Panda, P.R.; Kumar, A.)
Abstract	The need for hardware acceleration of Network-on-Chip (NoC) simulation has been motivated by their growing complexity and large design space. NoC simulation can exploit the inherent concurrency in hardware by using FPGA based emulators. For trace-driven NoC emulators, we enhance this raw hardware speedup by exploiting the traffic characteristics for a more efficient utilization of hardware. We propose a technique, OTO-NoC-Sim, to reduce NoC emulation time by scheduling network transactions in an out-of-time order. Our simulation technique addresses the challenges arising out of an out-of-time-order scheduling in maintaining the correctness of statistics measured. Our experiments indicate that our proposed technique reduces the average emulation time by 3× for multi-threaded applications and by 3.5× for multi-programmed benchmarks when compared to a conventional FPGA emulation.
Starting Page	315
Ending Page	324
File Size	951075
Page Count	10
File Format	PDF
ISBN	9781450307154
e-ISBN	9781450307154
DOI	10.1145/2039370.2039418
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-10-09
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Synchronization Emulation Hardware Field programmable gate arrays Transmitters Clocks Acceleration Trace-driven Simulation FPGA Emulation Hardware Acceleration Network-on-Chip Performance Analysis
Content Type	Text
Resource Type	Article

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