NDLI: Synthesizing a long latency unit within VLIW processor

Content Provider	IEEE Xplore Digital Library
Author	Gupta, R.L. Kumar, A. Van Der Werf, A. Busa, G.N.
Copyright Year	2001
Description	Author affiliation: Alliance Semicond., Bangalore, India (Gupta, R.L.)
Abstract	With increasing high performance requirements, VLIW processors are becoming more and more popular. To go beyond the performance achievable by the use of a VLIW architecture, specialized functional units can be added to the processor. However, no single tool provides the capability of synthesizing such a processor. This paper shows a method to embed a long latency unit within a VLIW processor datapath using some available tools. Phideo, an architectural synthesis tool is used to synthesize a special high throughput unit. The high level synthesis tool, Mistral2, is used to generate the VLIW processor datapath and to compile microcode for it. The Phideo synthesized unit is interfaced as a functional unit in the Mistral2 datapath and Mistral2 scheduling is made compatible with the Phideo schedule. The motion estimation algorithm for MPEG-2 standard has been chosen as a case study to prove the methodology.
Sponsorship	Broadcom India
Starting Page	460
Ending Page	465
File Size	574447
Page Count	6
File Format	PDF
ISBN	0769508316
ISSN	10639667
DOI	10.1109/ICVD.2001.902700
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-01-07
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay VLIW Throughput Hardware Coprocessors Processor scheduling Partitioning algorithms High level synthesis Motion estimation Telecommunications
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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